DFI Interface ecp5phy addr 13 bankbits 3 nranks 1 data 64 phases 4
nranks 1 nphases 2 addressbits 13
DFI Interface inti addr 13 bankbits 3 nranks 1 data 64 phases 2
DFI Interface slave addr 13 bankbits 3 nranks 1 data 64 phases 2
DFI Interface master addr 13 bankbits 3 nranks 1 data 64 phases 2
DFI Interface mem_dfi addr 13 bankbits 3 nranks 1 data 64 phases 2
clock domain sync2x_unbuf 200000000 0.01 0
clock domain init 25000000.0 0.01 1
clock domain dramsync2x_unbuf 200000000 0.01 2
PLL config {'clki_div': 1, 'clko0_freq': 200000000.0, 'clko0_div': 2, 'clko0_phase': 0, 'clko1_freq': 25000000.0, 'clko1_div': 16, 'clko1_phase': 0, 'clko2_freq': 200000000.0, 'clko2_div': 2, 'clko2_phase': 0, 'vco': 400000000.0, 'clkfb_div': 4}
params {'a_FREQUENCY_PIN_CLKI': '100.0', 'a_ICP_CURRENT': '6', 'a_LPF_RESISTOR': '16', 'a_MFG_ENABLE_FILTEROPAMP': '1', 'a_MFG_GMCREF_SEL': '2', 'p_FEEDBK_PATH': 'INT_OS3', 'p_CLKOS3_ENABLE': 'ENABLED', 'p_CLKOS3_DIV': 1, 'p_CLKFB_DIV': 4, 'p_CLKI_DIV': 1, 'i_RST': (~ (sig rst_0__i)), 'i_CLKI': (clk rawclk), 'o_LOCK': (sig $signal), 'p_CLKOP_ENABLE': 'ENABLED', 'p_CLKOP_DIV': 2, 'p_CLKOP_FPHASE': 0, 'p_CLKOP_CPHASE': 2, 'o_CLKOP': (clk sync2x_unbuf), 'p_CLKOS_ENABLE': 'ENABLED', 'p_CLKOS_DIV': 16, 'p_CLKOS_FPHASE': 0, 'p_CLKOS_CPHASE': 16, 'o_CLKOS': (clk init), 'p_CLKOS2_ENABLE': 'ENABLED', 'p_CLKOS2_DIV': 2, 'p_CLKOS2_FPHASE': 0, 'p_CLKOS2_CPHASE': 2, 'o_CLKOS2': (clk dramsync2x_unbuf)}
clock ras (rec ddr3_0__ras o_clk o_prst o_fclk o0 o1 o2 o3)
clock cas (rec ddr3_0__cas o_clk o_prst o_fclk o0 o1 o2 o3)
clock we (rec ddr3_0__we o_clk o_prst o_fclk o0 o1 o2 o3)
clock clk_en (rec ddr3_0__clk_en o_clk o_prst o_fclk o0 o1 o2 o3)
clock odt (rec ddr3_0__odt o_clk o_prst o_fclk o0 o1 o2 o3)
clock rst (rec ddr3_0__rst o_clk o_prst o_fclk o0 o1 o2 o3)
clock cs (rec ddr3_0__cs o_clk o_prst o_fclk o0 o1 o2 o3)
phase (rec inti address bank cas cs_n ras we clk_en odt reset act wrdata wrdata_en wrdata_mask rddata_en rddata rddata_valid)
phase (rec inti address bank cas cs_n ras we clk_en odt reset act wrdata wrdata_en wrdata_mask rddata_en rddata rddata_valid)

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.13 (git sha1 8b1eafc3a, clang 7.0.1-8+deb10u2 -fPIC -Os)


-- Executing script file `simsoc.ys' --

1. Executing RTLIL frontend.
Input filename: build_simsoc/top.il

2. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 980 redundant assignments.
Promoted 868 assignments to connections.

3. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `top.$group_7'.
Removing empty process `top.$group_6'.
Removing empty process `top.$group_5'.
Removing empty process `top.$group_4'.
Removing empty process `top.$group_3'.
Removing empty process `top.$group_2'.
Removing empty process `top.$group_1'.
Removing empty process `top.$group_0'.
Removing empty process `pin_rst_0.$group_0'.
Removing empty process `pin_ddr3_0__cas.$group_3'.
Removing empty process `pin_ddr3_0__cas.$group_2'.
Removing empty process `pin_ddr3_0__cas.$group_1'.
Removing empty process `pin_ddr3_0__cas.$group_0'.
Removing empty process `pin_ddr3_0__ras.$group_3'.
Removing empty process `pin_ddr3_0__ras.$group_2'.
Removing empty process `pin_ddr3_0__ras.$group_1'.
Removing empty process `pin_ddr3_0__ras.$group_0'.
Removing empty process `pin_ddr3_0__cs.$group_3'.
Removing empty process `pin_ddr3_0__cs.$group_2'.
Removing empty process `pin_ddr3_0__cs.$group_1'.
Removing empty process `pin_ddr3_0__cs.$group_0'.
Removing empty process `pin_ddr3_0__we.$group_3'.
Removing empty process `pin_ddr3_0__we.$group_2'.
Removing empty process `pin_ddr3_0__we.$group_1'.
Removing empty process `pin_ddr3_0__we.$group_0'.
Removing empty process `pin_ddr3_0__rst.$group_3'.
Removing empty process `pin_ddr3_0__rst.$group_2'.
Removing empty process `pin_ddr3_0__rst.$group_1'.
Removing empty process `pin_ddr3_0__rst.$group_0'.
Removing empty process `drambone.$group_4'.
Removing empty process `drambone.$group_0'.
Removing empty process `dramcore.$group_63'.
Removing empty process `dramcore.$group_62'.
Removing empty process `dramcore.$group_61'.
Removing empty process `dramcore.$group_60'.
Removing empty process `dramcore.$group_59'.
Removing empty process `dramcore.$group_58'.
Removing empty process `dramcore.$group_57'.
Removing empty process `dramcore.$group_56'.
Removing empty process `dramcore.$group_55'.
Removing empty process `dramcore.$group_54'.
Removing empty process `dramcore.$group_53'.
Removing empty process `dramcore.$group_52'.
Removing empty process `dramcore.$group_51'.
Removing empty process `dramcore.$group_50'.
Removing empty process `dramcore.$group_49'.
Removing empty process `dramcore.$group_48'.
Removing empty process `dramcore.$group_47'.
Removing empty process `dramcore.$group_46'.
Removing empty process `dramcore.$group_45'.
Removing empty process `dramcore.$group_44'.
Removing empty process `dramcore.$group_43'.
Removing empty process `dramcore.$group_42'.
Removing empty process `dramcore.$group_41'.
Removing empty process `dramcore.$group_40'.
Removing empty process `dramcore.$group_39'.
Removing empty process `dramcore.$group_38'.
Removing empty process `dramcore.$group_37'.
Removing empty process `dramcore.$group_36'.
Removing empty process `dramcore.$group_35'.
Removing empty process `dramcore.$group_34'.
Removing empty process `dramcore.$group_33'.
Removing empty process `dramcore.$group_32'.
Removing empty process `dramcore.$group_31'.
Removing empty process `dramcore.$group_30'.
Removing empty process `dramcore.$group_29'.
Removing empty process `dramcore.$group_28'.
Removing empty process `dramcore.$group_27'.
Removing empty process `dramcore.$group_26'.
Removing empty process `dramcore.$group_25'.
Removing empty process `dramcore.$group_24'.
Removing empty process `dramcore.$group_23'.
Removing empty process `dramcore.$group_22'.
Removing empty process `dramcore.$group_21'.
Removing empty process `dramcore.$group_20'.
Removing empty process `dramcore.$group_19'.
Removing empty process `dramcore.$group_18'.
Removing empty process `dramcore.$group_17'.
Removing empty process `dramcore.$group_16'.
Removing empty process `dramcore.$group_15'.
Removing empty process `dramcore.$group_14'.
Removing empty process `dramcore.$group_13'.
Removing empty process `dramcore.$group_12'.
Removing empty process `dramcore.$group_11'.
Removing empty process `dramcore.$group_10'.
Removing empty process `dramcore.$group_9'.
Removing empty process `dramcore.$group_8'.
Removing empty process `dramcore.$group_7'.
Removing empty process `dramcore.$group_6'.
Removing empty process `dramcore.$group_5'.
Removing empty process `dramcore.$group_4'.
Removing empty process `dramcore.$group_3'.
Removing empty process `dramcore.$group_2'.
Removing empty process `dramcore.$group_1'.
Removing empty process `dramcore.$group_0'.
Removing empty process `crossbar.$group_40'.
Removing empty process `crossbar.$group_37'.
Removing empty process `crossbar.$group_36'.
Removing empty process `crossbar.$group_35'.
Removing empty process `crossbar.$group_34'.
Removing empty process `crossbar.$group_33'.
Removing empty process `crossbar.$group_29'.
Removing empty process `crossbar.$group_25'.
Removing empty process `crossbar.$group_21'.
Removing empty process `crossbar.$group_17'.
Removing empty process `crossbar.$group_13'.
Removing empty process `crossbar.$group_9'.
Removing empty process `crossbar.$group_5'.
Removing empty process `crossbar.$group_1'.
Removing empty process `crossbar.$group_0'.
Removing empty process `U$$9.$group_1'.
Removing empty process `U$$8.$group_1'.
Removing empty process `controller.$group_55'.
Removing empty process `controller.$group_54'.
Removing empty process `controller.$group_53'.
Removing empty process `controller.$group_52'.
Removing empty process `controller.$group_51'.
Removing empty process `controller.$group_50'.
Removing empty process `controller.$group_49'.
Removing empty process `controller.$group_48'.
Removing empty process `controller.$group_47'.
Removing empty process `controller.$group_46'.
Removing empty process `controller.$group_45'.
Removing empty process `controller.$group_44'.
Removing empty process `controller.$group_43'.
Removing empty process `controller.$group_42'.
Removing empty process `controller.$group_41'.
Removing empty process `controller.$group_40'.
Removing empty process `controller.$group_39'.
Removing empty process `controller.$group_38'.
Removing empty process `controller.$group_37'.
Removing empty process `controller.$group_36'.
Removing empty process `controller.$group_35'.
Removing empty process `controller.$group_34'.
Removing empty process `controller.$group_33'.
Removing empty process `controller.$group_32'.
Removing empty process `controller.$group_31'.
Removing empty process `controller.$group_30'.
Removing empty process `controller.$group_29'.
Removing empty process `controller.$group_28'.
Removing empty process `controller.$group_27'.
Removing empty process `controller.$group_26'.
Removing empty process `controller.$group_25'.
Removing empty process `controller.$group_24'.
Removing empty process `controller.$group_23'.
Removing empty process `controller.$group_22'.
Removing empty process `controller.$group_21'.
Removing empty process `controller.$group_20'.
Removing empty process `controller.$group_19'.
Removing empty process `controller.$group_18'.
Removing empty process `controller.$group_17'.
Removing empty process `controller.$group_16'.
Removing empty process `controller.$group_15'.
Removing empty process `controller.$group_14'.
Removing empty process `controller.$group_13'.
Removing empty process `controller.$group_12'.
Removing empty process `controller.$group_11'.
Removing empty process `controller.$group_10'.
Removing empty process `controller.$group_9'.
Removing empty process `controller.$group_8'.
Removing empty process `controller.$group_7'.
Removing empty process `controller.$group_6'.
Removing empty process `controller.$group_5'.
Removing empty process `controller.$group_4'.
Removing empty process `controller.$group_3'.
Removing empty process `controller.$group_2'.
Removing empty process `controller.$group_1'.
Removing empty process `controller.$group_0'.
Found and cleaned up 2 empty switches in `\multiplexer.$group_36'.
Found and cleaned up 2 empty switches in `\multiplexer.$group_35'.
Found and cleaned up 2 empty switches in `\multiplexer.$group_34'.
Removing empty process `multiplexer.$group_28'.
Removing empty process `multiplexer.$group_26'.
Removing empty process `multiplexer.$group_25'.
Removing empty process `multiplexer.$group_24'.
Removing empty process `multiplexer.$group_23'.
Removing empty process `multiplexer.$group_22'.
Removing empty process `multiplexer.$group_21'.
Removing empty process `multiplexer.$group_20'.
Removing empty process `multiplexer.$group_19'.
Removing empty process `multiplexer.$group_18'.
Removing empty process `multiplexer.$group_17'.
Removing empty process `multiplexer.$group_16'.
Removing empty process `multiplexer.$group_15'.
Removing empty process `multiplexer.$group_14'.
Removing empty process `multiplexer.$group_13'.
Removing empty process `multiplexer.$group_12'.
Removing empty process `multiplexer.$group_11'.
Removing empty process `multiplexer.$group_10'.
Removing empty process `multiplexer.$group_9'.
Removing empty process `multiplexer.$group_8'.
Removing empty process `multiplexer.$group_7'.
Removing empty process `multiplexer.$group_6'.
Removing empty process `multiplexer.$group_5'.
Removing empty process `multiplexer.$group_4'.
Removing empty process `multiplexer.$group_3'.
Removing empty process `multiplexer.$group_2'.
Removing empty process `multiplexer.$group_1'.
Removing empty process `multiplexer.$group_0'.
Removing empty process `tfawcon.$group_1'.
Removing empty process `steerer.$group_13'.
Removing empty process `steerer.$group_12'.
Removing empty process `steerer.$group_11'.
Removing empty process `steerer.$group_2'.
Removing empty process `steerer.$group_1'.
Removing empty process `steerer.$group_0'.
Removing empty process `choose_req.$group_1'.
Removing empty process `choose_req.$group_0'.
Removing empty process `choose_cmd.$group_1'.
Removing empty process `choose_cmd.$group_0'.
Removing empty process `bankmachine7.$group_22'.
Removing empty process `bankmachine7.$group_21'.
Removing empty process `bankmachine7.$group_20'.
Removing empty process `bankmachine7.$group_19'.
Removing empty process `bankmachine7.$group_17'.
Removing empty process `bankmachine7.$group_14'.
Removing empty process `bankmachine7.$group_13'.
Removing empty process `bankmachine7.$group_12'.
Removing empty process `bankmachine7.$group_11'.
Removing empty process `bankmachine7.$group_10'.
Removing empty process `bankmachine7.$group_9'.
Removing empty process `bankmachine7.$group_8'.
Removing empty process `bankmachine7.$group_7'.
Removing empty process `bankmachine7.$group_6'.
Removing empty process `bankmachine7.$group_5'.
Removing empty process `bankmachine7.$group_4'.
Removing empty process `bankmachine7.$group_3'.
Removing empty process `bankmachine7.$group_2'.
Removing empty process `bankmachine7.$group_1'.
Removing empty process `bankmachine7.$group_0'.
Removing empty process `U$$1$62.$group_5'.
Removing empty process `U$$0$60.$group_16'.
Removing empty process `U$$0$60.$group_14'.
Removing empty process `U$$0$60.$group_13'.
Removing empty process `U$$0$60.$group_12'.
Removing empty process `U$$0$60.$group_11'.
Removing empty process `U$$0$60.$group_9'.
Removing empty process `U$$0$60.$group_8'.
Removing empty process `U$$0$60.$group_7'.
Removing empty process `U$$0$60.$group_6'.
Removing empty process `U$$0$60.$group_5'.
Removing empty process `U$$0$60.$group_1'.
Removing empty process `U$$0$60.$group_0'.
Removing empty process `fifo$61.$group_9'.
Removing empty process `fifo$61.$group_8'.
Removing empty process `fifo$61.$group_6'.
Removing empty process `fifo$61.$group_5'.
Removing empty process `fifo$61.$group_4'.
Removing empty process `fifo$61.$group_3'.
Removing empty process `fifo$61.$group_2'.
Removing empty process `fifo$61.$group_1'.
Removing empty process `fifo$61.$group_0'.
Removing empty process `current_slicer$56.$group_1'.
Removing empty process `current_slicer$56.$group_0'.
Removing empty process `lookahead_slicer$55.$group_1'.
Removing empty process `lookahead_slicer$55.$group_0'.
Removing empty process `bankmachine6.$group_22'.
Removing empty process `bankmachine6.$group_21'.
Removing empty process `bankmachine6.$group_20'.
Removing empty process `bankmachine6.$group_19'.
Removing empty process `bankmachine6.$group_17'.
Removing empty process `bankmachine6.$group_14'.
Removing empty process `bankmachine6.$group_13'.
Removing empty process `bankmachine6.$group_12'.
Removing empty process `bankmachine6.$group_11'.
Removing empty process `bankmachine6.$group_10'.
Removing empty process `bankmachine6.$group_9'.
Removing empty process `bankmachine6.$group_8'.
Removing empty process `bankmachine6.$group_7'.
Removing empty process `bankmachine6.$group_6'.
Removing empty process `bankmachine6.$group_5'.
Removing empty process `bankmachine6.$group_4'.
Removing empty process `bankmachine6.$group_3'.
Removing empty process `bankmachine6.$group_2'.
Removing empty process `bankmachine6.$group_1'.
Removing empty process `bankmachine6.$group_0'.
Removing empty process `U$$1$54.$group_5'.
Removing empty process `U$$0$52.$group_16'.
Removing empty process `U$$0$52.$group_14'.
Removing empty process `U$$0$52.$group_13'.
Removing empty process `U$$0$52.$group_12'.
Removing empty process `U$$0$52.$group_11'.
Removing empty process `U$$0$52.$group_9'.
Removing empty process `U$$0$52.$group_8'.
Removing empty process `U$$0$52.$group_7'.
Removing empty process `U$$0$52.$group_6'.
Removing empty process `U$$0$52.$group_5'.
Removing empty process `U$$0$52.$group_1'.
Removing empty process `U$$0$52.$group_0'.
Removing empty process `fifo$53.$group_9'.
Removing empty process `fifo$53.$group_8'.
Removing empty process `fifo$53.$group_6'.
Removing empty process `fifo$53.$group_5'.
Removing empty process `fifo$53.$group_4'.
Removing empty process `fifo$53.$group_3'.
Removing empty process `fifo$53.$group_2'.
Removing empty process `fifo$53.$group_1'.
Removing empty process `fifo$53.$group_0'.
Removing empty process `current_slicer$48.$group_1'.
Removing empty process `current_slicer$48.$group_0'.
Removing empty process `lookahead_slicer$47.$group_1'.
Removing empty process `lookahead_slicer$47.$group_0'.
Removing empty process `bankmachine5.$group_22'.
Removing empty process `bankmachine5.$group_21'.
Removing empty process `bankmachine5.$group_20'.
Removing empty process `bankmachine5.$group_19'.
Removing empty process `bankmachine5.$group_17'.
Removing empty process `bankmachine5.$group_14'.
Removing empty process `bankmachine5.$group_13'.
Removing empty process `bankmachine5.$group_12'.
Removing empty process `bankmachine5.$group_11'.
Removing empty process `bankmachine5.$group_10'.
Removing empty process `bankmachine5.$group_9'.
Removing empty process `bankmachine5.$group_8'.
Removing empty process `bankmachine5.$group_7'.
Removing empty process `bankmachine5.$group_6'.
Removing empty process `bankmachine5.$group_5'.
Removing empty process `bankmachine5.$group_4'.
Removing empty process `bankmachine5.$group_3'.
Removing empty process `bankmachine5.$group_2'.
Removing empty process `bankmachine5.$group_1'.
Removing empty process `bankmachine5.$group_0'.
Removing empty process `U$$1$46.$group_5'.
Removing empty process `U$$0$44.$group_16'.
Removing empty process `U$$0$44.$group_14'.
Removing empty process `U$$0$44.$group_13'.
Removing empty process `U$$0$44.$group_12'.
Removing empty process `U$$0$44.$group_11'.
Removing empty process `U$$0$44.$group_9'.
Removing empty process `U$$0$44.$group_8'.
Removing empty process `U$$0$44.$group_7'.
Removing empty process `U$$0$44.$group_6'.
Removing empty process `U$$0$44.$group_5'.
Removing empty process `U$$0$44.$group_1'.
Removing empty process `U$$0$44.$group_0'.
Removing empty process `fifo$45.$group_9'.
Removing empty process `fifo$45.$group_8'.
Removing empty process `fifo$45.$group_6'.
Removing empty process `fifo$45.$group_5'.
Removing empty process `fifo$45.$group_4'.
Removing empty process `fifo$45.$group_3'.
Removing empty process `fifo$45.$group_2'.
Removing empty process `fifo$45.$group_1'.
Removing empty process `fifo$45.$group_0'.
Removing empty process `current_slicer$40.$group_1'.
Removing empty process `current_slicer$40.$group_0'.
Removing empty process `lookahead_slicer$39.$group_1'.
Removing empty process `lookahead_slicer$39.$group_0'.
Removing empty process `bankmachine4.$group_22'.
Removing empty process `bankmachine4.$group_21'.
Removing empty process `bankmachine4.$group_20'.
Removing empty process `bankmachine4.$group_19'.
Removing empty process `bankmachine4.$group_17'.
Removing empty process `bankmachine4.$group_14'.
Removing empty process `bankmachine4.$group_13'.
Removing empty process `bankmachine4.$group_12'.
Removing empty process `bankmachine4.$group_11'.
Removing empty process `bankmachine4.$group_10'.
Removing empty process `bankmachine4.$group_9'.
Removing empty process `bankmachine4.$group_8'.
Removing empty process `bankmachine4.$group_7'.
Removing empty process `bankmachine4.$group_6'.
Removing empty process `bankmachine4.$group_5'.
Removing empty process `bankmachine4.$group_4'.
Removing empty process `bankmachine4.$group_3'.
Removing empty process `bankmachine4.$group_2'.
Removing empty process `bankmachine4.$group_1'.
Removing empty process `bankmachine4.$group_0'.
Removing empty process `U$$1$38.$group_5'.
Removing empty process `U$$0$36.$group_16'.
Removing empty process `U$$0$36.$group_14'.
Removing empty process `U$$0$36.$group_13'.
Removing empty process `U$$0$36.$group_12'.
Removing empty process `U$$0$36.$group_11'.
Removing empty process `U$$0$36.$group_9'.
Removing empty process `U$$0$36.$group_8'.
Removing empty process `U$$0$36.$group_7'.
Removing empty process `U$$0$36.$group_6'.
Removing empty process `U$$0$36.$group_5'.
Removing empty process `U$$0$36.$group_1'.
Removing empty process `U$$0$36.$group_0'.
Removing empty process `fifo$37.$group_9'.
Removing empty process `fifo$37.$group_8'.
Removing empty process `fifo$37.$group_6'.
Removing empty process `fifo$37.$group_5'.
Removing empty process `fifo$37.$group_4'.
Removing empty process `fifo$37.$group_3'.
Removing empty process `fifo$37.$group_2'.
Removing empty process `fifo$37.$group_1'.
Removing empty process `fifo$37.$group_0'.
Removing empty process `current_slicer$32.$group_1'.
Removing empty process `current_slicer$32.$group_0'.
Removing empty process `lookahead_slicer$31.$group_1'.
Removing empty process `lookahead_slicer$31.$group_0'.
Removing empty process `bankmachine3.$group_22'.
Removing empty process `bankmachine3.$group_21'.
Removing empty process `bankmachine3.$group_20'.
Removing empty process `bankmachine3.$group_19'.
Removing empty process `bankmachine3.$group_17'.
Removing empty process `bankmachine3.$group_14'.
Removing empty process `bankmachine3.$group_13'.
Removing empty process `bankmachine3.$group_12'.
Removing empty process `bankmachine3.$group_11'.
Removing empty process `bankmachine3.$group_10'.
Removing empty process `bankmachine3.$group_9'.
Removing empty process `bankmachine3.$group_8'.
Removing empty process `bankmachine3.$group_7'.
Removing empty process `bankmachine3.$group_6'.
Removing empty process `bankmachine3.$group_5'.
Removing empty process `bankmachine3.$group_4'.
Removing empty process `bankmachine3.$group_3'.
Removing empty process `bankmachine3.$group_2'.
Removing empty process `bankmachine3.$group_1'.
Removing empty process `bankmachine3.$group_0'.
Removing empty process `U$$1$30.$group_5'.
Removing empty process `U$$0$28.$group_16'.
Removing empty process `U$$0$28.$group_14'.
Removing empty process `U$$0$28.$group_13'.
Removing empty process `U$$0$28.$group_12'.
Removing empty process `U$$0$28.$group_11'.
Removing empty process `U$$0$28.$group_9'.
Removing empty process `U$$0$28.$group_8'.
Removing empty process `U$$0$28.$group_7'.
Removing empty process `U$$0$28.$group_6'.
Removing empty process `U$$0$28.$group_5'.
Removing empty process `U$$0$28.$group_1'.
Removing empty process `U$$0$28.$group_0'.
Removing empty process `fifo$29.$group_9'.
Removing empty process `fifo$29.$group_8'.
Removing empty process `fifo$29.$group_6'.
Removing empty process `fifo$29.$group_5'.
Removing empty process `fifo$29.$group_4'.
Removing empty process `fifo$29.$group_3'.
Removing empty process `fifo$29.$group_2'.
Removing empty process `fifo$29.$group_1'.
Removing empty process `fifo$29.$group_0'.
Removing empty process `current_slicer$24.$group_1'.
Removing empty process `current_slicer$24.$group_0'.
Removing empty process `lookahead_slicer$23.$group_1'.
Removing empty process `lookahead_slicer$23.$group_0'.
Removing empty process `bankmachine2.$group_22'.
Removing empty process `bankmachine2.$group_21'.
Removing empty process `bankmachine2.$group_20'.
Removing empty process `bankmachine2.$group_19'.
Removing empty process `bankmachine2.$group_17'.
Removing empty process `bankmachine2.$group_14'.
Removing empty process `bankmachine2.$group_13'.
Removing empty process `bankmachine2.$group_12'.
Removing empty process `bankmachine2.$group_11'.
Removing empty process `bankmachine2.$group_10'.
Removing empty process `bankmachine2.$group_9'.
Removing empty process `bankmachine2.$group_8'.
Removing empty process `bankmachine2.$group_7'.
Removing empty process `bankmachine2.$group_6'.
Removing empty process `bankmachine2.$group_5'.
Removing empty process `bankmachine2.$group_4'.
Removing empty process `bankmachine2.$group_3'.
Removing empty process `bankmachine2.$group_2'.
Removing empty process `bankmachine2.$group_1'.
Removing empty process `bankmachine2.$group_0'.
Removing empty process `U$$1$22.$group_5'.
Removing empty process `U$$0$20.$group_16'.
Removing empty process `U$$0$20.$group_14'.
Removing empty process `U$$0$20.$group_13'.
Removing empty process `U$$0$20.$group_12'.
Removing empty process `U$$0$20.$group_11'.
Removing empty process `U$$0$20.$group_9'.
Removing empty process `U$$0$20.$group_8'.
Removing empty process `U$$0$20.$group_7'.
Removing empty process `U$$0$20.$group_6'.
Removing empty process `U$$0$20.$group_5'.
Removing empty process `U$$0$20.$group_1'.
Removing empty process `U$$0$20.$group_0'.
Removing empty process `fifo$21.$group_9'.
Removing empty process `fifo$21.$group_8'.
Removing empty process `fifo$21.$group_6'.
Removing empty process `fifo$21.$group_5'.
Removing empty process `fifo$21.$group_4'.
Removing empty process `fifo$21.$group_3'.
Removing empty process `fifo$21.$group_2'.
Removing empty process `fifo$21.$group_1'.
Removing empty process `fifo$21.$group_0'.
Removing empty process `current_slicer$16.$group_1'.
Removing empty process `current_slicer$16.$group_0'.
Removing empty process `lookahead_slicer$15.$group_1'.
Removing empty process `lookahead_slicer$15.$group_0'.
Removing empty process `bankmachine1.$group_22'.
Removing empty process `bankmachine1.$group_21'.
Removing empty process `bankmachine1.$group_20'.
Removing empty process `bankmachine1.$group_19'.
Removing empty process `bankmachine1.$group_17'.
Removing empty process `bankmachine1.$group_14'.
Removing empty process `bankmachine1.$group_13'.
Removing empty process `bankmachine1.$group_12'.
Removing empty process `bankmachine1.$group_11'.
Removing empty process `bankmachine1.$group_10'.
Removing empty process `bankmachine1.$group_9'.
Removing empty process `bankmachine1.$group_8'.
Removing empty process `bankmachine1.$group_7'.
Removing empty process `bankmachine1.$group_6'.
Removing empty process `bankmachine1.$group_5'.
Removing empty process `bankmachine1.$group_4'.
Removing empty process `bankmachine1.$group_3'.
Removing empty process `bankmachine1.$group_2'.
Removing empty process `bankmachine1.$group_1'.
Removing empty process `bankmachine1.$group_0'.
Removing empty process `U$$1$14.$group_5'.
Removing empty process `U$$0$12.$group_16'.
Removing empty process `U$$0$12.$group_14'.
Removing empty process `U$$0$12.$group_13'.
Removing empty process `U$$0$12.$group_12'.
Removing empty process `U$$0$12.$group_11'.
Removing empty process `U$$0$12.$group_9'.
Removing empty process `U$$0$12.$group_8'.
Removing empty process `U$$0$12.$group_7'.
Removing empty process `U$$0$12.$group_6'.
Removing empty process `U$$0$12.$group_5'.
Removing empty process `U$$0$12.$group_1'.
Removing empty process `U$$0$12.$group_0'.
Removing empty process `fifo$13.$group_9'.
Removing empty process `fifo$13.$group_8'.
Removing empty process `fifo$13.$group_6'.
Removing empty process `fifo$13.$group_5'.
Removing empty process `fifo$13.$group_4'.
Removing empty process `fifo$13.$group_3'.
Removing empty process `fifo$13.$group_2'.
Removing empty process `fifo$13.$group_1'.
Removing empty process `fifo$13.$group_0'.
Removing empty process `current_slicer$8.$group_1'.
Removing empty process `current_slicer$8.$group_0'.
Removing empty process `lookahead_slicer$7.$group_1'.
Removing empty process `lookahead_slicer$7.$group_0'.
Removing empty process `bankmachine0.$group_22'.
Removing empty process `bankmachine0.$group_21'.
Removing empty process `bankmachine0.$group_20'.
Removing empty process `bankmachine0.$group_19'.
Removing empty process `bankmachine0.$group_17'.
Removing empty process `bankmachine0.$group_14'.
Removing empty process `bankmachine0.$group_13'.
Removing empty process `bankmachine0.$group_12'.
Removing empty process `bankmachine0.$group_11'.
Removing empty process `bankmachine0.$group_10'.
Removing empty process `bankmachine0.$group_9'.
Removing empty process `bankmachine0.$group_8'.
Removing empty process `bankmachine0.$group_7'.
Removing empty process `bankmachine0.$group_6'.
Removing empty process `bankmachine0.$group_5'.
Removing empty process `bankmachine0.$group_4'.
Removing empty process `bankmachine0.$group_3'.
Removing empty process `bankmachine0.$group_2'.
Removing empty process `bankmachine0.$group_1'.
Removing empty process `bankmachine0.$group_0'.
Removing empty process `U$$1$6.$group_5'.
Removing empty process `U$$0.$group_16'.
Removing empty process `U$$0.$group_14'.
Removing empty process `U$$0.$group_13'.
Removing empty process `U$$0.$group_12'.
Removing empty process `U$$0.$group_11'.
Removing empty process `U$$0.$group_9'.
Removing empty process `U$$0.$group_8'.
Removing empty process `U$$0.$group_7'.
Removing empty process `U$$0.$group_6'.
Removing empty process `U$$0.$group_5'.
Removing empty process `U$$0.$group_1'.
Removing empty process `U$$0.$group_0'.
Removing empty process `fifo.$group_9'.
Removing empty process `fifo.$group_8'.
Removing empty process `fifo.$group_6'.
Removing empty process `fifo.$group_5'.
Removing empty process `fifo.$group_4'.
Removing empty process `fifo.$group_3'.
Removing empty process `fifo.$group_2'.
Removing empty process `fifo.$group_1'.
Removing empty process `fifo.$group_0'.
Removing empty process `current_slicer.$group_1'.
Removing empty process `current_slicer.$group_0'.
Removing empty process `lookahead_slicer.$group_1'.
Removing empty process `lookahead_slicer.$group_0'.
Removing empty process `refresher.$group_13'.
Removing empty process `refresher.$group_12'.
Removing empty process `refresher.$group_11'.
Removing empty process `refresher.$group_10'.
Removing empty process `refresher.$group_9'.
Removing empty process `refresher.$group_3'.
Removing empty process `refresher.$group_2'.
Removing empty process `refresher.$group_1'.
Removing empty process `refresher.$group_0'.
Removing empty process `zqcs_executer.$group_0'.
Removing empty process `sequencer.$group_9'.
Removing empty process `sequencer.$group_8'.
Removing empty process `sequencer.$group_4'.
Removing empty process `sequencer.$group_3'.
Removing empty process `sequencer.$group_2'.
Removing empty process `sequencer.$group_1'.
Removing empty process `sequencer.$group_0'.
Removing empty process `executer.$group_0'.
Removing empty process `dfii.$group_41'.
Removing empty process `dfii.$group_40'.
Removing empty process `dfii.$group_39'.
Removing empty process `dfii.$group_38'.
Removing empty process `dfii.$group_37'.
Removing empty process `dfii.$group_36'.
Removing empty process `phase_1.$group_5'.
Removing empty process `phase_1.$group_4'.
Removing empty process `phase_1.$group_3'.
Removing empty process `phase_1.$group_2'.
Removing empty process `phase_1.$group_1'.
Removing empty process `phase_1.$group_0'.
Removing empty process `phase_0.$group_5'.
Removing empty process `phase_0.$group_4'.
Removing empty process `phase_0.$group_3'.
Removing empty process `phase_0.$group_2'.
Removing empty process `phase_0.$group_1'.
Removing empty process `phase_0.$group_0'.
Removing empty process `wb_decoder$4.$group_7'.
Removing empty process `wb_decoder$4.$group_4'.
Removing empty process `wb_decoder$4.$group_3'.
Removing empty process `wb_decoder$4.$group_2'.
Removing empty process `wb_decoder$4.$group_1'.
Removing empty process `wb_decoder$4.$group_0'.
Removing empty process `csr_bridge_0$3.$group_1'.
Removing empty process `csr_bridge_0$3.$group_0'.
Removing empty process `csr_mux_0$2.$group_39'.
Removing empty process `csr_mux_0$2.$group_33'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_32'.
Removing empty process `csr_mux_0$2.$group_30'.
Found and cleaned up 2 empty switches in `\csr_mux_0$2.$group_29'.
Removing empty process `csr_mux_0$2.$group_27'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_26'.
Removing empty process `csr_mux_0$2.$group_24'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_23'.
Removing empty process `csr_mux_0$2.$group_21'.
Removing empty process `csr_mux_0$2.$group_15'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_14'.
Removing empty process `csr_mux_0$2.$group_12'.
Found and cleaned up 2 empty switches in `\csr_mux_0$2.$group_11'.
Removing empty process `csr_mux_0$2.$group_9'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_8'.
Removing empty process `csr_mux_0$2.$group_6'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_5'.
Removing empty process `csr_mux_0$2.$group_3'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_2'.
Removing empty process `csr_mux_0$2.$group_0'.
Removing empty process `ddrphy.$group_144'.
Removing empty process `ddrphy.$group_143'.
Removing empty process `ddrphy.$group_142'.
Removing empty process `ddrphy.$group_141'.
Removing empty process `ddrphy.$group_140'.
Removing empty process `ddrphy.$group_138'.
Removing empty process `ddrphy.$group_137'.
Removing empty process `ddrphy.$group_136'.
Removing empty process `ddrphy.$group_135'.
Removing empty process `ddrphy.$group_134'.
Removing empty process `ddrphy.$group_132'.
Removing empty process `ddrphy.$group_130'.
Removing empty process `ddrphy.$group_127'.
Removing empty process `ddrphy.$group_124'.
Removing empty process `ddrphy.$group_121'.
Removing empty process `ddrphy.$group_118'.
Removing empty process `ddrphy.$group_115'.
Removing empty process `ddrphy.$group_112'.
Removing empty process `ddrphy.$group_109'.
Removing empty process `ddrphy.$group_106'.
Removing empty process `ddrphy.$group_103'.
Removing empty process `ddrphy.$group_99'.
Removing empty process `ddrphy.$group_96'.
Removing empty process `ddrphy.$group_93'.
Removing empty process `ddrphy.$group_90'.
Removing empty process `ddrphy.$group_87'.
Removing empty process `ddrphy.$group_84'.
Removing empty process `ddrphy.$group_81'.
Removing empty process `ddrphy.$group_76'.
Removing empty process `ddrphy.$group_73'.
Removing empty process `ddrphy.$group_71'.
Removing empty process `ddrphy.$group_70'.
Removing empty process `ddrphy.$group_69'.
Removing empty process `ddrphy.$group_68'.
Removing empty process `ddrphy.$group_67'.
Removing empty process `ddrphy.$group_66'.
Removing empty process `ddrphy.$group_65'.
Removing empty process `ddrphy.$group_64'.
Removing empty process `ddrphy.$group_63'.
Removing empty process `ddrphy.$group_62'.
Removing empty process `ddrphy.$group_61'.
Removing empty process `ddrphy.$group_60'.
Removing empty process `ddrphy.$group_59'.
Removing empty process `ddrphy.$group_58'.
Removing empty process `ddrphy.$group_57'.
Removing empty process `ddrphy.$group_56'.
Removing empty process `ddrphy.$group_55'.
Removing empty process `ddrphy.$group_54'.
Removing empty process `ddrphy.$group_53'.
Removing empty process `ddrphy.$group_52'.
Removing empty process `ddrphy.$group_51'.
Removing empty process `ddrphy.$group_50'.
Removing empty process `ddrphy.$group_49'.
Removing empty process `ddrphy.$group_48'.
Removing empty process `ddrphy.$group_47'.
Removing empty process `ddrphy.$group_46'.
Removing empty process `ddrphy.$group_45'.
Removing empty process `ddrphy.$group_44'.
Removing empty process `ddrphy.$group_43'.
Removing empty process `ddrphy.$group_42'.
Removing empty process `ddrphy.$group_41'.
Removing empty process `ddrphy.$group_40'.
Removing empty process `ddrphy.$group_39'.
Removing empty process `ddrphy.$group_38'.
Removing empty process `ddrphy.$group_37'.
Removing empty process `ddrphy.$group_36'.
Removing empty process `ddrphy.$group_35'.
Removing empty process `ddrphy.$group_34'.
Removing empty process `ddrphy.$group_33'.
Removing empty process `ddrphy.$group_32'.
Removing empty process `ddrphy.$group_31'.
Removing empty process `ddrphy.$group_30'.
Removing empty process `ddrphy.$group_29'.
Removing empty process `ddrphy.$group_28'.
Removing empty process `ddrphy.$group_27'.
Removing empty process `ddrphy.$group_26'.
Removing empty process `ddrphy.$group_25'.
Removing empty process `ddrphy.$group_24'.
Removing empty process `ddrphy.$group_23'.
Removing empty process `ddrphy.$group_22'.
Removing empty process `ddrphy.$group_21'.
Removing empty process `ddrphy.$group_20'.
Removing empty process `ddrphy.$group_19'.
Removing empty process `ddrphy.$group_18'.
Removing empty process `ddrphy.$group_17'.
Removing empty process `ddrphy.$group_16'.
Removing empty process `ddrphy.$group_15'.
Removing empty process `ddrphy.$group_14'.
Removing empty process `ddrphy.$group_13'.
Removing empty process `ddrphy.$group_12'.
Removing empty process `ddrphy.$group_11'.
Removing empty process `ddrphy.$group_10'.
Removing empty process `ddrphy.$group_9'.
Removing empty process `ddrphy.$group_8'.
Removing empty process `ddrphy.$group_7'.
Removing empty process `ddrphy.$group_6'.
Removing empty process `ddrphy.$group_5'.
Removing empty process `ddrphy.$group_4'.
Removing empty process `ddrphy.$group_3'.
Removing empty process `ddrphy.$group_2'.
Removing empty process `ddrphy.$group_0'.
Removing empty process `init.$group_1'.
Removing empty process `U$$1.$group_2'.
Removing empty process `wb_decoder.$group_7'.
Removing empty process `wb_decoder.$group_4'.
Removing empty process `wb_decoder.$group_3'.
Removing empty process `wb_decoder.$group_2'.
Removing empty process `wb_decoder.$group_1'.
Removing empty process `wb_decoder.$group_0'.
Removing empty process `csr_bridge_0.$group_1'.
Removing empty process `csr_bridge_0.$group_0'.
Removing empty process `csr_mux_0.$group_20'.
Found and cleaned up 3 empty switches in `\csr_mux_0.$group_19'.
Removing empty process `csr_mux_0.$group_16'.
Found and cleaned up 3 empty switches in `\csr_mux_0.$group_14'.
Removing empty process `csr_mux_0.$group_11'.
Found and cleaned up 3 empty switches in `\csr_mux_0.$group_9'.
Removing empty process `csr_mux_0.$group_6'.
Found and cleaned up 3 empty switches in `\csr_mux_0.$group_4'.
Removing empty process `csr_mux_0.$group_1'.
Removing empty process `decoder.$group_19'.
Removing empty process `decoder.$group_14'.
Removing empty process `decoder.$group_13'.
Removing empty process `decoder.$group_12'.
Removing empty process `decoder.$group_11'.
Removing empty process `decoder.$group_10'.
Removing empty process `decoder.$group_9'.
Removing empty process `decoder.$group_8'.
Removing empty process `decoder.$group_7'.
Removing empty process `decoder.$group_6'.
Removing empty process `decoder.$group_5'.
Removing empty process `decoder.$group_4'.
Removing empty process `decoder.$group_3'.
Removing empty process `decoder.$group_2'.
Removing empty process `decoder.$group_1'.
Removing empty process `decoder.$group_0'.
Removing empty process `sysclk.$group_6'.
Removing empty process `sysclk.$group_5'.
Removing empty process `sysclk.$group_4'.
Removing empty process `sysclk.$group_3'.
Removing empty process `sysclk.$group_0'.
Cleaned up 43 empty switches.

4. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $group_1 in module drambone.
Marked 1 switch rules as full_case in process $group_9 in module drambone.
Marked 1 switch rules as full_case in process $group_39 in module crossbar.
Marked 1 switch rules as full_case in process $group_24 in module crossbar.
Marked 1 switch rules as full_case in process $group_23 in module crossbar.
Marked 1 switch rules as full_case in process $group_22 in module crossbar.
Marked 1 switch rules as full_case in process $group_32 in module crossbar.
Marked 1 switch rules as full_case in process $group_20 in module crossbar.
Marked 1 switch rules as full_case in process $group_19 in module crossbar.
Marked 1 switch rules as full_case in process $group_18 in module crossbar.
Marked 1 switch rules as full_case in process $group_31 in module crossbar.
Marked 1 switch rules as full_case in process $group_16 in module crossbar.
Marked 1 switch rules as full_case in process $group_15 in module crossbar.
Marked 1 switch rules as full_case in process $group_14 in module crossbar.
Marked 1 switch rules as full_case in process $group_30 in module crossbar.
Marked 1 switch rules as full_case in process $group_12 in module crossbar.
Marked 1 switch rules as full_case in process $group_11 in module crossbar.
Marked 1 switch rules as full_case in process $group_10 in module crossbar.
Marked 1 switch rules as full_case in process $group_38 in module crossbar.
Marked 1 switch rules as full_case in process $group_8 in module crossbar.
Marked 1 switch rules as full_case in process $group_7 in module crossbar.
Marked 1 switch rules as full_case in process $group_6 in module crossbar.
Marked 1 switch rules as full_case in process $group_28 in module crossbar.
Marked 1 switch rules as full_case in process $group_4 in module crossbar.
Marked 1 switch rules as full_case in process $group_3 in module crossbar.
Marked 1 switch rules as full_case in process $group_2 in module crossbar.
Marked 1 switch rules as full_case in process $group_27 in module crossbar.
Marked 1 switch rules as full_case in process $group_26 in module crossbar.
Marked 1 switch rules as full_case in process $group_37 in module multiplexer.
Marked 1 switch rules as full_case in process $group_1 in module write_antistarvation.
Marked 1 switch rules as full_case in process $group_1 in module read_antistarvation.
Marked 1 switch rules as full_case in process $group_2 in module tfawcon.
Marked 1 switch rules as full_case in process $group_15 in module steerer.
Marked 1 switch rules as full_case in process $group_21 in module steerer.
Marked 1 switch rules as full_case in process $group_20 in module steerer.
Marked 1 switch rules as full_case in process $group_19 in module steerer.
Marked 1 switch rules as full_case in process $group_10 in module steerer.
Marked 1 switch rules as full_case in process $group_9 in module steerer.
Marked 1 switch rules as full_case in process $group_8 in module steerer.
Marked 1 switch rules as full_case in process $group_7 in module steerer.
Marked 1 switch rules as full_case in process $group_6 in module steerer.
Marked 1 switch rules as full_case in process $group_5 in module steerer.
Marked 1 switch rules as full_case in process $group_4 in module steerer.
Marked 1 switch rules as full_case in process $group_18 in module steerer.
Marked 1 switch rules as full_case in process $group_17 in module steerer.
Marked 1 switch rules as full_case in process $group_16 in module steerer.
Marked 1 switch rules as full_case in process $group_9 in module choose_req.
Marked 1 switch rules as full_case in process $group_8 in module choose_req.
Marked 1 switch rules as full_case in process $group_7 in module choose_req.
Marked 1 switch rules as full_case in process $group_6 in module choose_req.
Marked 1 switch rules as full_case in process $group_5 in module choose_req.
Marked 1 switch rules as full_case in process $group_4 in module choose_req.
Marked 1 switch rules as full_case in process $group_3 in module choose_req.
Marked 1 switch rules as full_case in process $group_2 in module choose_req.
Marked 1 switch rules as full_case in process $group_10 in module choose_req.
Marked 1 switch rules as full_case in process $group_0 in module arbiter$63.
Marked 1 switch rules as full_case in process $group_9 in module choose_cmd.
Marked 1 switch rules as full_case in process $group_8 in module choose_cmd.
Marked 1 switch rules as full_case in process $group_7 in module choose_cmd.
Marked 1 switch rules as full_case in process $group_6 in module choose_cmd.
Marked 1 switch rules as full_case in process $group_5 in module choose_cmd.
Marked 1 switch rules as full_case in process $group_4 in module choose_cmd.
Marked 1 switch rules as full_case in process $group_3 in module choose_cmd.
Marked 1 switch rules as full_case in process $group_2 in module choose_cmd.
Marked 1 switch rules as full_case in process $group_10 in module choose_cmd.
Marked 1 switch rules as full_case in process $group_0 in module arbiter.
Marked 1 switch rules as full_case in process $group_31 in module bankmachine7.
Marked 1 switch rules as full_case in process $group_30 in module bankmachine7.
Marked 4 switch rules as full_case in process $group_24 in module bankmachine7.
Marked 1 switch rules as full_case in process $group_18 in module bankmachine7.
Marked 1 switch rules as full_case in process $group_31 in module bankmachine6.
Marked 1 switch rules as full_case in process $group_30 in module bankmachine6.
Marked 4 switch rules as full_case in process $group_24 in module bankmachine6.
Marked 1 switch rules as full_case in process $group_18 in module bankmachine6.
Marked 1 switch rules as full_case in process $group_31 in module bankmachine5.
Marked 1 switch rules as full_case in process $group_30 in module bankmachine5.
Marked 4 switch rules as full_case in process $group_24 in module bankmachine5.
Marked 1 switch rules as full_case in process $group_18 in module bankmachine5.
Marked 1 switch rules as full_case in process $group_31 in module bankmachine4.
Marked 1 switch rules as full_case in process $group_30 in module bankmachine4.
Marked 4 switch rules as full_case in process $group_24 in module bankmachine4.
Marked 1 switch rules as full_case in process $group_18 in module bankmachine4.
Marked 1 switch rules as full_case in process $group_31 in module bankmachine3.
Marked 1 switch rules as full_case in process $group_30 in module bankmachine3.
Marked 4 switch rules as full_case in process $group_24 in module bankmachine3.
Marked 1 switch rules as full_case in process $group_18 in module bankmachine3.
Marked 1 switch rules as full_case in process $group_31 in module bankmachine2.
Marked 1 switch rules as full_case in process $group_30 in module bankmachine2.
Marked 4 switch rules as full_case in process $group_24 in module bankmachine2.
Marked 1 switch rules as full_case in process $group_18 in module bankmachine2.
Marked 1 switch rules as full_case in process $group_31 in module bankmachine1.
Marked 1 switch rules as full_case in process $group_30 in module bankmachine1.
Marked 4 switch rules as full_case in process $group_24 in module bankmachine1.
Marked 1 switch rules as full_case in process $group_18 in module bankmachine1.
Marked 1 switch rules as full_case in process $group_31 in module bankmachine0.
Marked 1 switch rules as full_case in process $group_30 in module bankmachine0.
Marked 4 switch rules as full_case in process $group_24 in module bankmachine0.
Marked 1 switch rules as full_case in process $group_18 in module bankmachine0.
Marked 2 switch rules as full_case in process $group_4 in module refresher.
Marked 2 switch rules as full_case in process $group_8 in module refresher.
Marked 1 switch rules as full_case in process $group_5 in module refresher.
Marked 1 switch rules as full_case in process $group_0 in module timeline$5.
Marked 1 switch rules as full_case in process $group_1 in module zqcs_timer.
Marked 1 switch rules as full_case in process $group_0 in module zqcs_timer.
Marked 1 switch rules as full_case in process $group_7 in module sequencer.
Marked 1 switch rules as full_case in process $group_6 in module sequencer.
Marked 1 switch rules as full_case in process $group_0 in module timeline.
Marked 2 switch rules as full_case in process $group_1 in module postponer.
Marked 1 switch rules as full_case in process $group_0 in module postponer.
Marked 1 switch rules as full_case in process $group_1 in module timer.
Marked 1 switch rules as full_case in process $group_0 in module timer.
Marked 1 switch rules as full_case in process $group_35 in module dfii.
Marked 1 switch rules as full_case in process $group_34 in module dfii.
Marked 1 switch rules as full_case in process $group_33 in module dfii.
Marked 1 switch rules as full_case in process $group_32 in module dfii.
Marked 1 switch rules as full_case in process $group_29 in module dfii.
Marked 1 switch rules as full_case in process $group_28 in module dfii.
Marked 1 switch rules as full_case in process $group_27 in module dfii.
Marked 1 switch rules as full_case in process $group_26 in module dfii.
Marked 1 switch rules as full_case in process $group_25 in module dfii.
Marked 1 switch rules as full_case in process $group_24 in module dfii.
Marked 1 switch rules as full_case in process $group_23 in module dfii.
Marked 1 switch rules as full_case in process $group_22 in module dfii.
Marked 1 switch rules as full_case in process $group_21 in module dfii.
Marked 1 switch rules as full_case in process $group_20 in module dfii.
Marked 1 switch rules as full_case in process $group_19 in module dfii.
Marked 1 switch rules as full_case in process $group_18 in module dfii.
Marked 1 switch rules as full_case in process $group_17 in module dfii.
Marked 1 switch rules as full_case in process $group_16 in module dfii.
Marked 1 switch rules as full_case in process $group_13 in module dfii.
Marked 1 switch rules as full_case in process $group_12 in module dfii.
Marked 1 switch rules as full_case in process $group_11 in module dfii.
Marked 1 switch rules as full_case in process $group_10 in module dfii.
Marked 1 switch rules as full_case in process $group_9 in module dfii.
Marked 1 switch rules as full_case in process $group_8 in module dfii.
Marked 1 switch rules as full_case in process $group_7 in module dfii.
Marked 1 switch rules as full_case in process $group_6 in module dfii.
Marked 1 switch rules as full_case in process $group_5 in module dfii.
Marked 1 switch rules as full_case in process $group_4 in module dfii.
Marked 1 switch rules as full_case in process $group_3 in module dfii.
Marked 1 switch rules as full_case in process $group_2 in module dfii.
Marked 1 switch rules as full_case in process $group_1 in module dfii.
Marked 1 switch rules as full_case in process $group_0 in module dfii.
Marked 1 switch rules as full_case in process $group_9 in module phase_1.
Marked 1 switch rules as full_case in process $group_8 in module phase_1.
Marked 1 switch rules as full_case in process $group_7 in module phase_1.
Marked 1 switch rules as full_case in process $group_6 in module phase_1.
Marked 1 switch rules as full_case in process $group_9 in module phase_0.
Marked 1 switch rules as full_case in process $group_8 in module phase_0.
Marked 1 switch rules as full_case in process $group_7 in module phase_0.
Marked 1 switch rules as full_case in process $group_6 in module phase_0.
Marked 1 switch rules as full_case in process $group_7 in module csr_bridge_0$3.
Marked 1 switch rules as full_case in process $group_6 in module csr_bridge_0$3.
Marked 1 switch rules as full_case in process $group_89 in module ddrphy.
Marked 1 switch rules as full_case in process $group_86 in module ddrphy.
Marked 1 switch rules as full_case in process $group_120 in module ddrphy.
Marked 1 switch rules as full_case in process $group_83 in module ddrphy.
Marked 1 switch rules as full_case in process $group_78 in module ddrphy.
Marked 1 switch rules as full_case in process $group_75 in module ddrphy.
Marked 1 switch rules as full_case in process $group_117 in module ddrphy.
Marked 1 switch rules as full_case in process $group_114 in module ddrphy.
Marked 1 switch rules as full_case in process $group_129 in module ddrphy.
Marked 1 switch rules as full_case in process $group_111 in module ddrphy.
Marked 1 switch rules as full_case in process $group_108 in module ddrphy.
Marked 1 switch rules as full_case in process $group_105 in module ddrphy.
Marked 1 switch rules as full_case in process $group_126 in module ddrphy.
Marked 1 switch rules as full_case in process $group_101 in module ddrphy.
Marked 1 switch rules as full_case in process $group_98 in module ddrphy.
Marked 1 switch rules as full_case in process $group_95 in module ddrphy.
Marked 1 switch rules as full_case in process $group_123 in module ddrphy.
Marked 1 switch rules as full_case in process $group_92 in module ddrphy.
Marked 1 switch rules as full_case in process $group_0 in module U$$2.
Marked 1 switch rules as full_case in process $group_7 in module csr_bridge_0.
Marked 1 switch rules as full_case in process $group_6 in module csr_bridge_0.
Removed a total of 0 dead cases.

5. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\drambone.$group_9'.
  Set init value: \fsm_state = 2'00
Found init rule in `\U$$9.$group_0'.
  Set init value: \buffer = 14'00000000000000
Found init rule in `\U$$8.$group_0'.
  Set init value: \buffer = 4'0000
Found init rule in `\U$$7.$group_0'.
  Set init value: \valid = 1'0
Found init rule in `\U$$6.$group_0'.
  Set init value: \valid = 1'0
Found init rule in `\U$$5.$group_0'.
  Set init value: \valid = 1'0
Found init rule in `\U$$4.$group_0'.
  Set init value: \valid = 1'0
Found init rule in `\U$$3.$group_0'.
  Set init value: \valid = 1'0
Found init rule in `\U$$2$66.$group_0'.
  Set init value: \valid = 1'0
Found init rule in `\U$$1$65.$group_0'.
  Set init value: \valid = 1'0
Found init rule in `\U$$0$64.$group_0'.
  Set init value: \valid = 1'0
Found init rule in `\multiplexer.$group_37'.
  Set init value: \fsm_state = 4'0000
Found init rule in `\write_antistarvation.$group_1'.
  Set init value: \max_time = 1'1
Found init rule in `\write_antistarvation.$group_0'.
  Set init value: \time = 4'0000
Found init rule in `\read_antistarvation.$group_1'.
  Set init value: \max_time = 1'1
Found init rule in `\read_antistarvation.$group_0'.
  Set init value: \time = 5'00000
Found init rule in `\twtrcon.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\twtrcon.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\tccdcon.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\tccdcon.$group_0'.
  Set init value: \count = 1'0
Found init rule in `\tfawcon.$group_2'.
  Set init value: \ready = 1'1
Found init rule in `\tfawcon.$group_0'.
  Set init value: \window = 5'00000
Found init rule in `\trrdcon.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trrdcon.$group_0'.
  Set init value: \count = 1'0
Found init rule in `\steerer.$group_15'.
  Set init value: \mem_dfi__bank$2 = 3'000
Found init rule in `\steerer.$group_14'.
  Set init value: \mem_dfi__cs_n$4 = 1'1
Found init rule in `\steerer.$group_21'.
  Set init value: \mem_dfi__wrdata_en$10 = 1'0
Found init rule in `\steerer.$group_20'.
  Set init value: \mem_dfi__rddata_en$11 = 1'0
Found init rule in `\steerer.$group_19'.
  Set init value: \mem_dfi__we$6 = 1'1
Found init rule in `\steerer.$group_10'.
  Set init value: \mem_dfi__wrdata_en = 1'0
Found init rule in `\steerer.$group_9'.
  Set init value: \mem_dfi__rddata_en = 1'0
Found init rule in `\steerer.$group_8'.
  Set init value: \mem_dfi__we = 1'1
Found init rule in `\steerer.$group_7'.
  Set init value: \mem_dfi__ras = 1'1
Found init rule in `\steerer.$group_6'.
  Set init value: \mem_dfi__cas = 1'1
Found init rule in `\steerer.$group_5'.
  Set init value: \mem_dfi__address = 13'0000000000000
Found init rule in `\steerer.$group_4'.
  Set init value: \mem_dfi__bank = 3'000
Found init rule in `\steerer.$group_3'.
  Set init value: \mem_dfi__cs_n = 1'1
Found init rule in `\steerer.$group_18'.
  Set init value: \mem_dfi__ras$5 = 1'1
Found init rule in `\steerer.$group_17'.
  Set init value: \mem_dfi__cas$3 = 1'1
Found init rule in `\steerer.$group_16'.
  Set init value: \mem_dfi__address$1 = 13'0000000000000
Found init rule in `\arbiter$63.$group_1'.
  Set init value: \valid = 1'0
Found init rule in `\arbiter$63.$group_0'.
  Set init value: \grant = 3'000
Found init rule in `\arbiter.$group_1'.
  Set init value: \valid = 1'0
Found init rule in `\arbiter.$group_0'.
  Set init value: \grant = 3'000
Found init rule in `\bankmachine7.$group_16'.
  Set init value: \row = 13'0000000000000
Found init rule in `\bankmachine7.$group_15'.
  Set init value: \row_opened = 1'0
Found init rule in `\bankmachine7.$group_24'.
  Set init value: \fsm_state = 3'000
Found init rule in `\U$$1$62.$group_3'.
  Set init value: \source__payload__we = 1'0
  Set init value: \source__payload__addr = 20'00000000000000000000
Found init rule in `\U$$1$62.$group_2'.
  Set init value: \source__last = 1'0
Found init rule in `\U$$1$62.$group_1'.
  Set init value: \source__first = 1'0
Found init rule in `\U$$1$62.$group_0'.
  Set init value: \source__valid = 1'0
Found init rule in `\fifo$61.$group_10'.
  Set init value: \consume = 3'000
Found init rule in `\fifo$61.$group_7'.
  Set init value: \produce = 3'000
Found init rule in `\fifo$61.$group_11'.
  Set init value: \level = 4'0000
Found init rule in `\trascon$59.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trascon$59.$group_0'.
  Set init value: \count = 2'00
Found init rule in `\trccon$58.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trccon$58.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\twtpcon$57.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\twtpcon$57.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\bankmachine6.$group_16'.
  Set init value: \row = 13'0000000000000
Found init rule in `\bankmachine6.$group_15'.
  Set init value: \row_opened = 1'0
Found init rule in `\bankmachine6.$group_24'.
  Set init value: \fsm_state = 3'000
Found init rule in `\U$$1$54.$group_3'.
  Set init value: \source__payload__we = 1'0
  Set init value: \source__payload__addr = 20'00000000000000000000
Found init rule in `\U$$1$54.$group_2'.
  Set init value: \source__last = 1'0
Found init rule in `\U$$1$54.$group_1'.
  Set init value: \source__first = 1'0
Found init rule in `\U$$1$54.$group_0'.
  Set init value: \source__valid = 1'0
Found init rule in `\fifo$53.$group_10'.
  Set init value: \consume = 3'000
Found init rule in `\fifo$53.$group_7'.
  Set init value: \produce = 3'000
Found init rule in `\fifo$53.$group_11'.
  Set init value: \level = 4'0000
Found init rule in `\trascon$51.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trascon$51.$group_0'.
  Set init value: \count = 2'00
Found init rule in `\trccon$50.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trccon$50.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\twtpcon$49.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\twtpcon$49.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\bankmachine5.$group_16'.
  Set init value: \row = 13'0000000000000
Found init rule in `\bankmachine5.$group_15'.
  Set init value: \row_opened = 1'0
Found init rule in `\bankmachine5.$group_24'.
  Set init value: \fsm_state = 3'000
Found init rule in `\U$$1$46.$group_3'.
  Set init value: \source__payload__we = 1'0
  Set init value: \source__payload__addr = 20'00000000000000000000
Found init rule in `\U$$1$46.$group_2'.
  Set init value: \source__last = 1'0
Found init rule in `\U$$1$46.$group_1'.
  Set init value: \source__first = 1'0
Found init rule in `\U$$1$46.$group_0'.
  Set init value: \source__valid = 1'0
Found init rule in `\fifo$45.$group_10'.
  Set init value: \consume = 3'000
Found init rule in `\fifo$45.$group_7'.
  Set init value: \produce = 3'000
Found init rule in `\fifo$45.$group_11'.
  Set init value: \level = 4'0000
Found init rule in `\trascon$43.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trascon$43.$group_0'.
  Set init value: \count = 2'00
Found init rule in `\trccon$42.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trccon$42.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\twtpcon$41.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\twtpcon$41.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\bankmachine4.$group_16'.
  Set init value: \row = 13'0000000000000
Found init rule in `\bankmachine4.$group_15'.
  Set init value: \row_opened = 1'0
Found init rule in `\bankmachine4.$group_24'.
  Set init value: \fsm_state = 3'000
Found init rule in `\U$$1$38.$group_3'.
  Set init value: \source__payload__we = 1'0
  Set init value: \source__payload__addr = 20'00000000000000000000
Found init rule in `\U$$1$38.$group_2'.
  Set init value: \source__last = 1'0
Found init rule in `\U$$1$38.$group_1'.
  Set init value: \source__first = 1'0
Found init rule in `\U$$1$38.$group_0'.
  Set init value: \source__valid = 1'0
Found init rule in `\fifo$37.$group_10'.
  Set init value: \consume = 3'000
Found init rule in `\fifo$37.$group_7'.
  Set init value: \produce = 3'000
Found init rule in `\fifo$37.$group_11'.
  Set init value: \level = 4'0000
Found init rule in `\trascon$35.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trascon$35.$group_0'.
  Set init value: \count = 2'00
Found init rule in `\trccon$34.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trccon$34.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\twtpcon$33.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\twtpcon$33.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\bankmachine3.$group_16'.
  Set init value: \row = 13'0000000000000
Found init rule in `\bankmachine3.$group_15'.
  Set init value: \row_opened = 1'0
Found init rule in `\bankmachine3.$group_24'.
  Set init value: \fsm_state = 3'000
Found init rule in `\U$$1$30.$group_3'.
  Set init value: \source__payload__we = 1'0
  Set init value: \source__payload__addr = 20'00000000000000000000
Found init rule in `\U$$1$30.$group_2'.
  Set init value: \source__last = 1'0
Found init rule in `\U$$1$30.$group_1'.
  Set init value: \source__first = 1'0
Found init rule in `\U$$1$30.$group_0'.
  Set init value: \source__valid = 1'0
Found init rule in `\fifo$29.$group_10'.
  Set init value: \consume = 3'000
Found init rule in `\fifo$29.$group_7'.
  Set init value: \produce = 3'000
Found init rule in `\fifo$29.$group_11'.
  Set init value: \level = 4'0000
Found init rule in `\trascon$27.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trascon$27.$group_0'.
  Set init value: \count = 2'00
Found init rule in `\trccon$26.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trccon$26.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\twtpcon$25.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\twtpcon$25.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\bankmachine2.$group_16'.
  Set init value: \row = 13'0000000000000
Found init rule in `\bankmachine2.$group_15'.
  Set init value: \row_opened = 1'0
Found init rule in `\bankmachine2.$group_24'.
  Set init value: \fsm_state = 3'000
Found init rule in `\U$$1$22.$group_3'.
  Set init value: \source__payload__we = 1'0
  Set init value: \source__payload__addr = 20'00000000000000000000
Found init rule in `\U$$1$22.$group_2'.
  Set init value: \source__last = 1'0
Found init rule in `\U$$1$22.$group_1'.
  Set init value: \source__first = 1'0
Found init rule in `\U$$1$22.$group_0'.
  Set init value: \source__valid = 1'0
Found init rule in `\fifo$21.$group_10'.
  Set init value: \consume = 3'000
Found init rule in `\fifo$21.$group_7'.
  Set init value: \produce = 3'000
Found init rule in `\fifo$21.$group_11'.
  Set init value: \level = 4'0000
Found init rule in `\trascon$19.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trascon$19.$group_0'.
  Set init value: \count = 2'00
Found init rule in `\trccon$18.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trccon$18.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\twtpcon$17.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\twtpcon$17.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\bankmachine1.$group_16'.
  Set init value: \row = 13'0000000000000
Found init rule in `\bankmachine1.$group_15'.
  Set init value: \row_opened = 1'0
Found init rule in `\bankmachine1.$group_24'.
  Set init value: \fsm_state = 3'000
Found init rule in `\U$$1$14.$group_3'.
  Set init value: \source__payload__we = 1'0
  Set init value: \source__payload__addr = 20'00000000000000000000
Found init rule in `\U$$1$14.$group_2'.
  Set init value: \source__last = 1'0
Found init rule in `\U$$1$14.$group_1'.
  Set init value: \source__first = 1'0
Found init rule in `\U$$1$14.$group_0'.
  Set init value: \source__valid = 1'0
Found init rule in `\fifo$13.$group_10'.
  Set init value: \consume = 3'000
Found init rule in `\fifo$13.$group_7'.
  Set init value: \produce = 3'000
Found init rule in `\fifo$13.$group_11'.
  Set init value: \level = 4'0000
Found init rule in `\trascon$11.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trascon$11.$group_0'.
  Set init value: \count = 2'00
Found init rule in `\trccon$10.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trccon$10.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\twtpcon$9.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\twtpcon$9.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\bankmachine0.$group_16'.
  Set init value: \row = 13'0000000000000
Found init rule in `\bankmachine0.$group_15'.
  Set init value: \row_opened = 1'0
Found init rule in `\bankmachine0.$group_24'.
  Set init value: \fsm_state = 3'000
Found init rule in `\U$$1$6.$group_3'.
  Set init value: \source__payload__we = 1'0
  Set init value: \source__payload__addr = 20'00000000000000000000
Found init rule in `\U$$1$6.$group_2'.
  Set init value: \source__last = 1'0
Found init rule in `\U$$1$6.$group_1'.
  Set init value: \source__first = 1'0
Found init rule in `\U$$1$6.$group_0'.
  Set init value: \source__valid = 1'0
Found init rule in `\fifo.$group_10'.
  Set init value: \consume = 3'000
Found init rule in `\fifo.$group_7'.
  Set init value: \produce = 3'000
Found init rule in `\fifo.$group_11'.
  Set init value: \level = 4'0000
Found init rule in `\trascon.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trascon.$group_0'.
  Set init value: \count = 2'00
Found init rule in `\trccon.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\trccon.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\twtpcon.$group_1'.
  Set init value: \ready = 1'0
Found init rule in `\twtpcon.$group_0'.
  Set init value: \count = 3'000
Found init rule in `\refresher.$group_4'.
  Set init value: \fsm_state = 2'00
Found init rule in `\timeline$5.$group_6'.
  Set init value: \done = 1'0
Found init rule in `\timeline$5.$group_5'.
  Set init value: \we = 1'0
Found init rule in `\timeline$5.$group_4'.
  Set init value: \ras = 1'0
Found init rule in `\timeline$5.$group_3'.
  Set init value: \cas = 1'0
Found init rule in `\timeline$5.$group_2'.
  Set init value: \ba = 3'000
Found init rule in `\timeline$5.$group_1'.
  Set init value: \a = 13'0000000000000
Found init rule in `\timeline$5.$group_0'.
  Set init value: \counter = 6'000000
Found init rule in `\zqcs_timer.$group_1'.
  Set init value: \done = 1'0
Found init rule in `\zqcs_timer.$group_0'.
  Set init value: \count = 27'101111101011110000011111111
Found init rule in `\sequencer.$group_5'.
  Set init value: \count = 1'0
Found init rule in `\sequencer.$group_7'.
  Set init value: \countDiffZero = 1'0
Found init rule in `\sequencer.$group_6'.
  Set init value: \countEqZero = 1'1
Found init rule in `\timeline.$group_6'.
  Set init value: \done = 1'0
Found init rule in `\timeline.$group_5'.
  Set init value: \we = 1'0
Found init rule in `\timeline.$group_4'.
  Set init value: \ras = 1'0
Found init rule in `\timeline.$group_3'.
  Set init value: \cas = 1'0
Found init rule in `\timeline.$group_2'.
  Set init value: \ba = 3'000
Found init rule in `\timeline.$group_1'.
  Set init value: \a = 13'0000000000000
Found init rule in `\timeline.$group_0'.
  Set init value: \counter = 7'0000000
Found init rule in `\postponer.$group_1'.
  Set init value: \req_o = 1'0
Found init rule in `\postponer.$group_0'.
  Set init value: \count = 1'0
Found init rule in `\timer.$group_1'.
  Set init value: \done = 1'0
Found init rule in `\timer.$group_0'.
  Set init value: \count = 10'1100001101
Found init rule in `\phase_1.$group_10'.
  Set init value: \dfii_p1_rddata__r_data = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `\phase_0.$group_10'.
  Set init value: \dfii_p0_rddata__r_data = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `\csr_bridge_0$3.$group_5'.
  Set init value: \cycle = 3'000
Found init rule in `\csr_bridge_0$3.$group_7'.
  Set init value: \wb__ack = 1'0
Found init rule in `\csr_bridge_0$3.$group_6'.
  Set init value: \wb__dat_r = 0
Found init rule in `\csr_mux_0$2.$group_36'.
  Set init value: \dfii_p1_rddata__shadow_en = 8'00000000
Found init rule in `\csr_mux_0$2.$group_26'.
  Set init value: \dfii_p1_command_issue__shadow = 1'0
Found init rule in `\csr_mux_0$2.$group_25'.
  Set init value: \dfii_p1_command_issue__w_stb = 1'0
Found init rule in `\csr_mux_0$2.$group_35'.
  Set init value: \dfii_p1_wrdata__shadow = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `\csr_mux_0$2.$group_23'.
  Set init value: \dfii_p1_command__shadow = 6'000000
Found init rule in `\csr_mux_0$2.$group_22'.
  Set init value: \dfii_p1_command__w_stb = 1'0
Found init rule in `\csr_mux_0$2.$group_34'.
  Set init value: \dfii_p1_wrdata__w_stb = 1'0
Found init rule in `\csr_mux_0$2.$group_20'.
  Set init value: \dfii_p0_rddata__shadow = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `\csr_mux_0$2.$group_18'.
  Set init value: \dfii_p0_rddata__shadow_en = 8'00000000
Found init rule in `\csr_mux_0$2.$group_17'.
  Set init value: \dfii_p0_wrdata__shadow = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `\csr_mux_0$2.$group_16'.
  Set init value: \dfii_p0_wrdata__w_stb = 1'0
Found init rule in `\csr_mux_0$2.$group_38'.
  Set init value: \dfii_p1_rddata__shadow = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `\csr_mux_0$2.$group_14'.
  Set init value: \dfii_p0_baddress__shadow = 3'000
Found init rule in `\csr_mux_0$2.$group_13'.
  Set init value: \dfii_p0_baddress__w_stb = 1'0
Found init rule in `\csr_mux_0$2.$group_32'.
  Set init value: \dfii_p1_baddress__shadow = 3'000
Found init rule in `\csr_mux_0$2.$group_11'.
  Set init value: \dfii_p0_address__shadow = 13'0000000000000
Found init rule in `\csr_mux_0$2.$group_10'.
  Set init value: \dfii_p0_address__w_stb = 1'0
Found init rule in `\csr_mux_0$2.$group_31'.
  Set init value: \dfii_p1_baddress__w_stb = 1'0
Found init rule in `\csr_mux_0$2.$group_8'.
  Set init value: \dfii_p0_command_issue__shadow = 1'0
Found init rule in `\csr_mux_0$2.$group_7'.
  Set init value: \dfii_p0_command_issue__w_stb = 1'0
Found init rule in `\csr_mux_0$2.$group_5'.
  Set init value: \dfii_p0_command__shadow = 6'000000
Found init rule in `\csr_mux_0$2.$group_4'.
  Set init value: \dfii_p0_command__w_stb = 1'0
Found init rule in `\csr_mux_0$2.$group_29'.
  Set init value: \dfii_p1_address__shadow = 13'0000000000000
Found init rule in `\csr_mux_0$2.$group_2'.
  Set init value: \dfii_control__shadow = 4'0000
Found init rule in `\csr_mux_0$2.$group_1'.
  Set init value: \dfii_control__w_stb = 1'0
Found init rule in `\csr_mux_0$2.$group_28'.
  Set init value: \dfii_p1_address__w_stb = 1'0
Found init rule in `\ddrphy.$group_122'.
  Set init value: \dq_o_data_d$373 = 8'00000000
Found init rule in `\ddrphy.$group_89'.
  Set init value: \dq_o_data_muxed$48 = 4'0000
Found init rule in `\ddrphy.$group_88'.
  Set init value: \dq_o_data_d$351 = 8'00000000
Found init rule in `\ddrphy.$group_139'.
  Set init value: \wrdata_en_last = 7'0000000
Found init rule in `\ddrphy.$group_86'.
  Set init value: \dq_o_data_muxed$38 = 4'0000
Found init rule in `\ddrphy.$group_85'.
  Set init value: \dq_o_data_d$349 = 8'00000000
Found init rule in `\ddrphy.$group_120'.
  Set init value: \dq_o_data_muxed$159 = 4'0000
Found init rule in `\ddrphy.$group_83'.
  Set init value: \dq_o_data_muxed$28 = 4'0000
Found init rule in `\ddrphy.$group_82'.
  Set init value: \dq_o_data_d$347 = 8'00000000
Found init rule in `\ddrphy.$group_119'.
  Set init value: \dq_o_data_d$371 = 8'00000000
Found init rule in `\ddrphy.$group_80'.
  Set init value: \ecp5phy__rddata$12 = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `\ddrphy.$group_79'.
  Set init value: \ecp5phy__rddata = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `\ddrphy.$group_78'.
  Set init value: \dq_o_data_muxed = 4'0000
Found init rule in `\ddrphy.$group_77'.
  Set init value: \dq_o_data_d = 8'00000000
Found init rule in `\ddrphy.$group_131'.
  Set init value: \rddata_en_last = 13'0000000000000
Found init rule in `\ddrphy.$group_75'.
  Set init value: \dm_o_data_muxed = 4'0000
Found init rule in `\ddrphy.$group_74'.
  Set init value: \dm_o_data_d = 8'00000000
Found init rule in `\ddrphy.$group_117'.
  Set init value: \dq_o_data_muxed$149 = 4'0000
Found init rule in `\ddrphy.$group_72'.
  Set init value: \datavalid_prev = 1'0
Found init rule in `\ddrphy.$group_116'.
  Set init value: \dq_o_data_d$369 = 8'00000000
Found init rule in `\ddrphy.$group_145'.
  Set init value: $sample$s$burstdet$sync$1 = 1'0
Found init rule in `\ddrphy.$group_114'.
  Set init value: \dq_o_data_muxed$139 = 4'0000
Found init rule in `\ddrphy.$group_113'.
  Set init value: \dq_o_data_d$367 = 8'00000000
Found init rule in `\ddrphy.$group_129'.
  Set init value: \dq_o_data_muxed$189 = 4'0000
Found init rule in `\ddrphy.$group_111'.
  Set init value: \dq_o_data_muxed$129 = 4'0000
Found init rule in `\ddrphy.$group_110'.
  Set init value: \dq_o_data_d$365 = 8'00000000
Found init rule in `\ddrphy.$group_128'.
  Set init value: \dq_o_data_d$377 = 8'00000000
Found init rule in `\ddrphy.$group_108'.
  Set init value: \dq_o_data_muxed$119 = 4'0000
Found init rule in `\ddrphy.$group_107'.
  Set init value: \dq_o_data_d$363 = 8'00000000
Found init rule in `\ddrphy.$group_146'.
  Set init value: $sample$s$burstdet$sync$1$204 = 1'0
Found init rule in `\ddrphy.$group_105'.
  Set init value: \dm_o_data_muxed$108 = 4'0000
Found init rule in `\ddrphy.$group_104'.
  Set init value: \dm_o_data_d$361 = 8'00000000
Found init rule in `\ddrphy.$group_126'.
  Set init value: \dq_o_data_muxed$179 = 4'0000
Found init rule in `\ddrphy.$group_102'.
  Set init value: \datavalid_prev$250 = 1'0
Found init rule in `\ddrphy.$group_101'.
  Set init value: \dq_o_data_muxed$88 = 4'0000
Found init rule in `\ddrphy.$group_100'.
  Set init value: \dq_o_data_d$359 = 8'00000000
Found init rule in `\ddrphy.$group_125'.
  Set init value: \dq_o_data_d$375 = 8'00000000
Found init rule in `\ddrphy.$group_98'.
  Set init value: \dq_o_data_muxed$78 = 4'0000
Found init rule in `\ddrphy.$group_97'.
  Set init value: \dq_o_data_d$357 = 8'00000000
Found init rule in `\ddrphy.$group_133'.
  Set init value: \rddata_valid = 1'0
Found init rule in `\ddrphy.$group_95'.
  Set init value: \dq_o_data_muxed$68 = 4'0000
Found init rule in `\ddrphy.$group_94'.
  Set init value: \dq_o_data_d$355 = 8'00000000
Found init rule in `\ddrphy.$group_123'.
  Set init value: \dq_o_data_muxed$169 = 4'0000
Found init rule in `\ddrphy.$group_92'.
  Set init value: \dq_o_data_muxed$58 = 4'0000
Found init rule in `\ddrphy.$group_1'.
  Set init value: \burstdet_reg = 2'00
Found init rule in `\ddrphy.$group_91'.
  Set init value: \dq_o_data_d$353 = 8'00000000
Found init rule in `\dqsbufm_manager1.$group_2'.
  Set init value: \readclksel = 3'000
Found init rule in `\dqsbufm_manager1.$group_1'.
  Set init value: \fsm_state = 4'0000
Found init rule in `\dqsbufm_manager1.$group_0'.
  Set init value: \pause = 1'0
Found init rule in `\dqsbufm_manager0.$group_2'.
  Set init value: \readclksel = 3'000
Found init rule in `\dqsbufm_manager0.$group_1'.
  Set init value: \fsm_state = 4'0000
Found init rule in `\dqsbufm_manager0.$group_0'.
  Set init value: \pause = 1'0
Found init rule in `\init.$group_0'.
  Set init value: \lock_d = 1'0
Found init rule in `\U$$2.$group_5'.
  Set init value: \update = 1'0
Found init rule in `\U$$2.$group_4'.
  Set init value: \pause = 1'0
Found init rule in `\U$$2.$group_3'.
  Set init value: \reset = 1'0
Found init rule in `\U$$2.$group_2'.
  Set init value: \stop = 1'0
Found init rule in `\U$$2.$group_1'.
  Set init value: \freeze = 1'0
Found init rule in `\U$$2.$group_0'.
  Set init value: \counter = 7'0000000
Found init rule in `\U$$1.$group_1'.
  Set init value: \stage1 = 1'0
Found init rule in `\U$$1.$group_0'.
  Set init value: \stage0 = 1'0
Found init rule in `\csr_bridge_0.$group_5'.
  Set init value: \cycle = 3'000
Found init rule in `\csr_bridge_0.$group_7'.
  Set init value: \wb__ack = 1'0
Found init rule in `\csr_bridge_0.$group_6'.
  Set init value: \wb__dat_r = 0
Found init rule in `\csr_mux_0.$group_15'.
  Set init value: \bitslip__shadow_en = 4'0000
Found init rule in `\csr_mux_0.$group_14'.
  Set init value: \rdly_p1__shadow = 3'000
Found init rule in `\csr_mux_0.$group_12'.
  Set init value: \rdly_p1__w_stb = 1'0
Found init rule in `\csr_mux_0.$group_10'.
  Set init value: \rdly_p1__shadow_en = 4'0000
Found init rule in `\csr_mux_0.$group_9'.
  Set init value: \rdly_p0__shadow = 3'000
Found init rule in `\csr_mux_0.$group_7'.
  Set init value: \rdly_p0__w_stb = 1'0
Found init rule in `\csr_mux_0.$group_17'.
  Set init value: \bitslip__w_stb = 1'0
Found init rule in `\csr_mux_0.$group_5'.
  Set init value: \rdly_p0__shadow_en = 4'0000
Found init rule in `\csr_mux_0.$group_4'.
  Set init value: \burstdet__shadow = 2'00
Found init rule in `\csr_mux_0.$group_2'.
  Set init value: \burstdet__w_stb = 1'0
Found init rule in `\csr_mux_0.$group_19'.
  Set init value: \bitslip__shadow = 3'000
Found init rule in `\csr_mux_0.$group_0'.
  Set init value: \burstdet__shadow_en = 4'0000
Found init rule in `\sysclk.$group_1'.
  Set init value: \podcnt = 3'111
Found init rule in `\sysclk.$group_2'.
  Set init value: \pod_done = 1'0

6. Executing PROC_ARST pass (detect async resets in processes).

7. Executing PROC_DLATCH pass (convert process syncs to latches).

8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\drambone.\fsm_state' using process `\drambone.$group_9'.
  created $dff cell `$procdff$1' with positive edge clock.
Creating register for signal `\U$$9.\buffer' using process `\U$$9.$group_0'.
  created $dff cell `$procdff$2' with positive edge clock.
Creating register for signal `\U$$8.\buffer' using process `\U$$8.$group_0'.
  created $dff cell `$procdff$3' with positive edge clock.
Creating register for signal `\U$$7.\valid' using process `\U$$7.$group_0'.
  created $dff cell `$procdff$4' with positive edge clock.
Creating register for signal `\U$$6.\valid' using process `\U$$6.$group_0'.
  created $dff cell `$procdff$5' with positive edge clock.
Creating register for signal `\U$$5.\valid' using process `\U$$5.$group_0'.
  created $dff cell `$procdff$6' with positive edge clock.
Creating register for signal `\U$$4.\valid' using process `\U$$4.$group_0'.
  created $dff cell `$procdff$7' with positive edge clock.
Creating register for signal `\U$$3.\valid' using process `\U$$3.$group_0'.
  created $dff cell `$procdff$8' with positive edge clock.
Creating register for signal `\U$$2$66.\valid' using process `\U$$2$66.$group_0'.
  created $dff cell `$procdff$9' with positive edge clock.
Creating register for signal `\U$$1$65.\valid' using process `\U$$1$65.$group_0'.
  created $dff cell `$procdff$10' with positive edge clock.
Creating register for signal `\U$$0$64.\valid' using process `\U$$0$64.$group_0'.
  created $dff cell `$procdff$11' with positive edge clock.
Creating register for signal `\multiplexer.\fsm_state' using process `\multiplexer.$group_37'.
  created $dff cell `$procdff$12' with positive edge clock.
Creating register for signal `\write_antistarvation.\max_time' using process `\write_antistarvation.$group_1'.
  created $dff cell `$procdff$13' with positive edge clock.
Creating register for signal `\write_antistarvation.\time' using process `\write_antistarvation.$group_0'.
  created $dff cell `$procdff$14' with positive edge clock.
Creating register for signal `\read_antistarvation.\max_time' using process `\read_antistarvation.$group_1'.
  created $dff cell `$procdff$15' with positive edge clock.
Creating register for signal `\read_antistarvation.\time' using process `\read_antistarvation.$group_0'.
  created $dff cell `$procdff$16' with positive edge clock.
Creating register for signal `\twtrcon.\ready' using process `\twtrcon.$group_1'.
  created $dff cell `$procdff$17' with positive edge clock.
Creating register for signal `\twtrcon.\count' using process `\twtrcon.$group_0'.
  created $dff cell `$procdff$18' with positive edge clock.
Creating register for signal `\tccdcon.\ready' using process `\tccdcon.$group_1'.
  created $dff cell `$procdff$19' with positive edge clock.
Creating register for signal `\tccdcon.\count' using process `\tccdcon.$group_0'.
  created $dff cell `$procdff$20' with positive edge clock.
Creating register for signal `\tfawcon.\ready' using process `\tfawcon.$group_2'.
  created $dff cell `$procdff$21' with positive edge clock.
Creating register for signal `\tfawcon.\window' using process `\tfawcon.$group_0'.
  created $dff cell `$procdff$22' with positive edge clock.
Creating register for signal `\trrdcon.\ready' using process `\trrdcon.$group_1'.
  created $dff cell `$procdff$23' with positive edge clock.
Creating register for signal `\trrdcon.\count' using process `\trrdcon.$group_0'.
  created $dff cell `$procdff$24' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__bank$2' using process `\steerer.$group_15'.
  created $dff cell `$procdff$25' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__cs_n$4' using process `\steerer.$group_14'.
  created $dff cell `$procdff$26' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__wrdata_en$10' using process `\steerer.$group_21'.
  created $dff cell `$procdff$27' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__rddata_en$11' using process `\steerer.$group_20'.
  created $dff cell `$procdff$28' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__we$6' using process `\steerer.$group_19'.
  created $dff cell `$procdff$29' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__wrdata_en' using process `\steerer.$group_10'.
  created $dff cell `$procdff$30' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__rddata_en' using process `\steerer.$group_9'.
  created $dff cell `$procdff$31' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__we' using process `\steerer.$group_8'.
  created $dff cell `$procdff$32' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__ras' using process `\steerer.$group_7'.
  created $dff cell `$procdff$33' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__cas' using process `\steerer.$group_6'.
  created $dff cell `$procdff$34' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__address' using process `\steerer.$group_5'.
  created $dff cell `$procdff$35' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__bank' using process `\steerer.$group_4'.
  created $dff cell `$procdff$36' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__cs_n' using process `\steerer.$group_3'.
  created $dff cell `$procdff$37' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__ras$5' using process `\steerer.$group_18'.
  created $dff cell `$procdff$38' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__cas$3' using process `\steerer.$group_17'.
  created $dff cell `$procdff$39' with positive edge clock.
Creating register for signal `\steerer.\mem_dfi__address$1' using process `\steerer.$group_16'.
  created $dff cell `$procdff$40' with positive edge clock.
Creating register for signal `\arbiter$63.\valid' using process `\arbiter$63.$group_1'.
  created $dff cell `$procdff$41' with positive edge clock.
Creating register for signal `\arbiter$63.\grant' using process `\arbiter$63.$group_0'.
  created $dff cell `$procdff$42' with positive edge clock.
Creating register for signal `\arbiter.\valid' using process `\arbiter.$group_1'.
  created $dff cell `$procdff$43' with positive edge clock.
Creating register for signal `\arbiter.\grant' using process `\arbiter.$group_0'.
  created $dff cell `$procdff$44' with positive edge clock.
Creating register for signal `\bankmachine7.\row' using process `\bankmachine7.$group_16'.
  created $dff cell `$procdff$45' with positive edge clock.
Creating register for signal `\bankmachine7.\row_opened' using process `\bankmachine7.$group_15'.
  created $dff cell `$procdff$46' with positive edge clock.
Creating register for signal `\bankmachine7.\fsm_state' using process `\bankmachine7.$group_24'.
  created $dff cell `$procdff$47' with positive edge clock.
Creating register for signal `\U$$1$62.\source__payload__we' using process `\U$$1$62.$group_3'.
  created $dff cell `$procdff$48' with positive edge clock.
Creating register for signal `\U$$1$62.\source__payload__addr' using process `\U$$1$62.$group_3'.
  created $dff cell `$procdff$49' with positive edge clock.
Creating register for signal `\U$$1$62.\source__last' using process `\U$$1$62.$group_2'.
  created $dff cell `$procdff$50' with positive edge clock.
Creating register for signal `\U$$1$62.\source__first' using process `\U$$1$62.$group_1'.
  created $dff cell `$procdff$51' with positive edge clock.
Creating register for signal `\U$$1$62.\source__valid' using process `\U$$1$62.$group_0'.
  created $dff cell `$procdff$52' with positive edge clock.
Creating register for signal `\fifo$61.\consume' using process `\fifo$61.$group_10'.
  created $dff cell `$procdff$53' with positive edge clock.
Creating register for signal `\fifo$61.\produce' using process `\fifo$61.$group_7'.
  created $dff cell `$procdff$54' with positive edge clock.
Creating register for signal `\fifo$61.\level' using process `\fifo$61.$group_11'.
  created $dff cell `$procdff$55' with positive edge clock.
Creating register for signal `\trascon$59.\ready' using process `\trascon$59.$group_1'.
  created $dff cell `$procdff$56' with positive edge clock.
Creating register for signal `\trascon$59.\count' using process `\trascon$59.$group_0'.
  created $dff cell `$procdff$57' with positive edge clock.
Creating register for signal `\trccon$58.\ready' using process `\trccon$58.$group_1'.
  created $dff cell `$procdff$58' with positive edge clock.
Creating register for signal `\trccon$58.\count' using process `\trccon$58.$group_0'.
  created $dff cell `$procdff$59' with positive edge clock.
Creating register for signal `\twtpcon$57.\ready' using process `\twtpcon$57.$group_1'.
  created $dff cell `$procdff$60' with positive edge clock.
Creating register for signal `\twtpcon$57.\count' using process `\twtpcon$57.$group_0'.
  created $dff cell `$procdff$61' with positive edge clock.
Creating register for signal `\bankmachine6.\row' using process `\bankmachine6.$group_16'.
  created $dff cell `$procdff$62' with positive edge clock.
Creating register for signal `\bankmachine6.\row_opened' using process `\bankmachine6.$group_15'.
  created $dff cell `$procdff$63' with positive edge clock.
Creating register for signal `\bankmachine6.\fsm_state' using process `\bankmachine6.$group_24'.
  created $dff cell `$procdff$64' with positive edge clock.
Creating register for signal `\U$$1$54.\source__payload__we' using process `\U$$1$54.$group_3'.
  created $dff cell `$procdff$65' with positive edge clock.
Creating register for signal `\U$$1$54.\source__payload__addr' using process `\U$$1$54.$group_3'.
  created $dff cell `$procdff$66' with positive edge clock.
Creating register for signal `\U$$1$54.\source__last' using process `\U$$1$54.$group_2'.
  created $dff cell `$procdff$67' with positive edge clock.
Creating register for signal `\U$$1$54.\source__first' using process `\U$$1$54.$group_1'.
  created $dff cell `$procdff$68' with positive edge clock.
Creating register for signal `\U$$1$54.\source__valid' using process `\U$$1$54.$group_0'.
  created $dff cell `$procdff$69' with positive edge clock.
Creating register for signal `\fifo$53.\consume' using process `\fifo$53.$group_10'.
  created $dff cell `$procdff$70' with positive edge clock.
Creating register for signal `\fifo$53.\produce' using process `\fifo$53.$group_7'.
  created $dff cell `$procdff$71' with positive edge clock.
Creating register for signal `\fifo$53.\level' using process `\fifo$53.$group_11'.
  created $dff cell `$procdff$72' with positive edge clock.
Creating register for signal `\trascon$51.\ready' using process `\trascon$51.$group_1'.
  created $dff cell `$procdff$73' with positive edge clock.
Creating register for signal `\trascon$51.\count' using process `\trascon$51.$group_0'.
  created $dff cell `$procdff$74' with positive edge clock.
Creating register for signal `\trccon$50.\ready' using process `\trccon$50.$group_1'.
  created $dff cell `$procdff$75' with positive edge clock.
Creating register for signal `\trccon$50.\count' using process `\trccon$50.$group_0'.
  created $dff cell `$procdff$76' with positive edge clock.
Creating register for signal `\twtpcon$49.\ready' using process `\twtpcon$49.$group_1'.
  created $dff cell `$procdff$77' with positive edge clock.
Creating register for signal `\twtpcon$49.\count' using process `\twtpcon$49.$group_0'.
  created $dff cell `$procdff$78' with positive edge clock.
Creating register for signal `\bankmachine5.\row' using process `\bankmachine5.$group_16'.
  created $dff cell `$procdff$79' with positive edge clock.
Creating register for signal `\bankmachine5.\row_opened' using process `\bankmachine5.$group_15'.
  created $dff cell `$procdff$80' with positive edge clock.
Creating register for signal `\bankmachine5.\fsm_state' using process `\bankmachine5.$group_24'.
  created $dff cell `$procdff$81' with positive edge clock.
Creating register for signal `\U$$1$46.\source__payload__we' using process `\U$$1$46.$group_3'.
  created $dff cell `$procdff$82' with positive edge clock.
Creating register for signal `\U$$1$46.\source__payload__addr' using process `\U$$1$46.$group_3'.
  created $dff cell `$procdff$83' with positive edge clock.
Creating register for signal `\U$$1$46.\source__last' using process `\U$$1$46.$group_2'.
  created $dff cell `$procdff$84' with positive edge clock.
Creating register for signal `\U$$1$46.\source__first' using process `\U$$1$46.$group_1'.
  created $dff cell `$procdff$85' with positive edge clock.
Creating register for signal `\U$$1$46.\source__valid' using process `\U$$1$46.$group_0'.
  created $dff cell `$procdff$86' with positive edge clock.
Creating register for signal `\fifo$45.\consume' using process `\fifo$45.$group_10'.
  created $dff cell `$procdff$87' with positive edge clock.
Creating register for signal `\fifo$45.\produce' using process `\fifo$45.$group_7'.
  created $dff cell `$procdff$88' with positive edge clock.
Creating register for signal `\fifo$45.\level' using process `\fifo$45.$group_11'.
  created $dff cell `$procdff$89' with positive edge clock.
Creating register for signal `\trascon$43.\ready' using process `\trascon$43.$group_1'.
  created $dff cell `$procdff$90' with positive edge clock.
Creating register for signal `\trascon$43.\count' using process `\trascon$43.$group_0'.
  created $dff cell `$procdff$91' with positive edge clock.
Creating register for signal `\trccon$42.\ready' using process `\trccon$42.$group_1'.
  created $dff cell `$procdff$92' with positive edge clock.
Creating register for signal `\trccon$42.\count' using process `\trccon$42.$group_0'.
  created $dff cell `$procdff$93' with positive edge clock.
Creating register for signal `\twtpcon$41.\ready' using process `\twtpcon$41.$group_1'.
  created $dff cell `$procdff$94' with positive edge clock.
Creating register for signal `\twtpcon$41.\count' using process `\twtpcon$41.$group_0'.
  created $dff cell `$procdff$95' with positive edge clock.
Creating register for signal `\bankmachine4.\row' using process `\bankmachine4.$group_16'.
  created $dff cell `$procdff$96' with positive edge clock.
Creating register for signal `\bankmachine4.\row_opened' using process `\bankmachine4.$group_15'.
  created $dff cell `$procdff$97' with positive edge clock.
Creating register for signal `\bankmachine4.\fsm_state' using process `\bankmachine4.$group_24'.
  created $dff cell `$procdff$98' with positive edge clock.
Creating register for signal `\U$$1$38.\source__payload__we' using process `\U$$1$38.$group_3'.
  created $dff cell `$procdff$99' with positive edge clock.
Creating register for signal `\U$$1$38.\source__payload__addr' using process `\U$$1$38.$group_3'.
  created $dff cell `$procdff$100' with positive edge clock.
Creating register for signal `\U$$1$38.\source__last' using process `\U$$1$38.$group_2'.
  created $dff cell `$procdff$101' with positive edge clock.
Creating register for signal `\U$$1$38.\source__first' using process `\U$$1$38.$group_1'.
  created $dff cell `$procdff$102' with positive edge clock.
Creating register for signal `\U$$1$38.\source__valid' using process `\U$$1$38.$group_0'.
  created $dff cell `$procdff$103' with positive edge clock.
Creating register for signal `\fifo$37.\consume' using process `\fifo$37.$group_10'.
  created $dff cell `$procdff$104' with positive edge clock.
Creating register for signal `\fifo$37.\produce' using process `\fifo$37.$group_7'.
  created $dff cell `$procdff$105' with positive edge clock.
Creating register for signal `\fifo$37.\level' using process `\fifo$37.$group_11'.
  created $dff cell `$procdff$106' with positive edge clock.
Creating register for signal `\trascon$35.\ready' using process `\trascon$35.$group_1'.
  created $dff cell `$procdff$107' with positive edge clock.
Creating register for signal `\trascon$35.\count' using process `\trascon$35.$group_0'.
  created $dff cell `$procdff$108' with positive edge clock.
Creating register for signal `\trccon$34.\ready' using process `\trccon$34.$group_1'.
  created $dff cell `$procdff$109' with positive edge clock.
Creating register for signal `\trccon$34.\count' using process `\trccon$34.$group_0'.
  created $dff cell `$procdff$110' with positive edge clock.
Creating register for signal `\twtpcon$33.\ready' using process `\twtpcon$33.$group_1'.
  created $dff cell `$procdff$111' with positive edge clock.
Creating register for signal `\twtpcon$33.\count' using process `\twtpcon$33.$group_0'.
  created $dff cell `$procdff$112' with positive edge clock.
Creating register for signal `\bankmachine3.\row' using process `\bankmachine3.$group_16'.
  created $dff cell `$procdff$113' with positive edge clock.
Creating register for signal `\bankmachine3.\row_opened' using process `\bankmachine3.$group_15'.
  created $dff cell `$procdff$114' with positive edge clock.
Creating register for signal `\bankmachine3.\fsm_state' using process `\bankmachine3.$group_24'.
  created $dff cell `$procdff$115' with positive edge clock.
Creating register for signal `\U$$1$30.\source__payload__we' using process `\U$$1$30.$group_3'.
  created $dff cell `$procdff$116' with positive edge clock.
Creating register for signal `\U$$1$30.\source__payload__addr' using process `\U$$1$30.$group_3'.
  created $dff cell `$procdff$117' with positive edge clock.
Creating register for signal `\U$$1$30.\source__last' using process `\U$$1$30.$group_2'.
  created $dff cell `$procdff$118' with positive edge clock.
Creating register for signal `\U$$1$30.\source__first' using process `\U$$1$30.$group_1'.
  created $dff cell `$procdff$119' with positive edge clock.
Creating register for signal `\U$$1$30.\source__valid' using process `\U$$1$30.$group_0'.
  created $dff cell `$procdff$120' with positive edge clock.
Creating register for signal `\fifo$29.\consume' using process `\fifo$29.$group_10'.
  created $dff cell `$procdff$121' with positive edge clock.
Creating register for signal `\fifo$29.\produce' using process `\fifo$29.$group_7'.
  created $dff cell `$procdff$122' with positive edge clock.
Creating register for signal `\fifo$29.\level' using process `\fifo$29.$group_11'.
  created $dff cell `$procdff$123' with positive edge clock.
Creating register for signal `\trascon$27.\ready' using process `\trascon$27.$group_1'.
  created $dff cell `$procdff$124' with positive edge clock.
Creating register for signal `\trascon$27.\count' using process `\trascon$27.$group_0'.
  created $dff cell `$procdff$125' with positive edge clock.
Creating register for signal `\trccon$26.\ready' using process `\trccon$26.$group_1'.
  created $dff cell `$procdff$126' with positive edge clock.
Creating register for signal `\trccon$26.\count' using process `\trccon$26.$group_0'.
  created $dff cell `$procdff$127' with positive edge clock.
Creating register for signal `\twtpcon$25.\ready' using process `\twtpcon$25.$group_1'.
  created $dff cell `$procdff$128' with positive edge clock.
Creating register for signal `\twtpcon$25.\count' using process `\twtpcon$25.$group_0'.
  created $dff cell `$procdff$129' with positive edge clock.
Creating register for signal `\bankmachine2.\row' using process `\bankmachine2.$group_16'.
  created $dff cell `$procdff$130' with positive edge clock.
Creating register for signal `\bankmachine2.\row_opened' using process `\bankmachine2.$group_15'.
  created $dff cell `$procdff$131' with positive edge clock.
Creating register for signal `\bankmachine2.\fsm_state' using process `\bankmachine2.$group_24'.
  created $dff cell `$procdff$132' with positive edge clock.
Creating register for signal `\U$$1$22.\source__payload__we' using process `\U$$1$22.$group_3'.
  created $dff cell `$procdff$133' with positive edge clock.
Creating register for signal `\U$$1$22.\source__payload__addr' using process `\U$$1$22.$group_3'.
  created $dff cell `$procdff$134' with positive edge clock.
Creating register for signal `\U$$1$22.\source__last' using process `\U$$1$22.$group_2'.
  created $dff cell `$procdff$135' with positive edge clock.
Creating register for signal `\U$$1$22.\source__first' using process `\U$$1$22.$group_1'.
  created $dff cell `$procdff$136' with positive edge clock.
Creating register for signal `\U$$1$22.\source__valid' using process `\U$$1$22.$group_0'.
  created $dff cell `$procdff$137' with positive edge clock.
Creating register for signal `\fifo$21.\consume' using process `\fifo$21.$group_10'.
  created $dff cell `$procdff$138' with positive edge clock.
Creating register for signal `\fifo$21.\produce' using process `\fifo$21.$group_7'.
  created $dff cell `$procdff$139' with positive edge clock.
Creating register for signal `\fifo$21.\level' using process `\fifo$21.$group_11'.
  created $dff cell `$procdff$140' with positive edge clock.
Creating register for signal `\trascon$19.\ready' using process `\trascon$19.$group_1'.
  created $dff cell `$procdff$141' with positive edge clock.
Creating register for signal `\trascon$19.\count' using process `\trascon$19.$group_0'.
  created $dff cell `$procdff$142' with positive edge clock.
Creating register for signal `\trccon$18.\ready' using process `\trccon$18.$group_1'.
  created $dff cell `$procdff$143' with positive edge clock.
Creating register for signal `\trccon$18.\count' using process `\trccon$18.$group_0'.
  created $dff cell `$procdff$144' with positive edge clock.
Creating register for signal `\twtpcon$17.\ready' using process `\twtpcon$17.$group_1'.
  created $dff cell `$procdff$145' with positive edge clock.
Creating register for signal `\twtpcon$17.\count' using process `\twtpcon$17.$group_0'.
  created $dff cell `$procdff$146' with positive edge clock.
Creating register for signal `\bankmachine1.\row' using process `\bankmachine1.$group_16'.
  created $dff cell `$procdff$147' with positive edge clock.
Creating register for signal `\bankmachine1.\row_opened' using process `\bankmachine1.$group_15'.
  created $dff cell `$procdff$148' with positive edge clock.
Creating register for signal `\bankmachine1.\fsm_state' using process `\bankmachine1.$group_24'.
  created $dff cell `$procdff$149' with positive edge clock.
Creating register for signal `\U$$1$14.\source__payload__we' using process `\U$$1$14.$group_3'.
  created $dff cell `$procdff$150' with positive edge clock.
Creating register for signal `\U$$1$14.\source__payload__addr' using process `\U$$1$14.$group_3'.
  created $dff cell `$procdff$151' with positive edge clock.
Creating register for signal `\U$$1$14.\source__last' using process `\U$$1$14.$group_2'.
  created $dff cell `$procdff$152' with positive edge clock.
Creating register for signal `\U$$1$14.\source__first' using process `\U$$1$14.$group_1'.
  created $dff cell `$procdff$153' with positive edge clock.
Creating register for signal `\U$$1$14.\source__valid' using process `\U$$1$14.$group_0'.
  created $dff cell `$procdff$154' with positive edge clock.
Creating register for signal `\fifo$13.\consume' using process `\fifo$13.$group_10'.
  created $dff cell `$procdff$155' with positive edge clock.
Creating register for signal `\fifo$13.\produce' using process `\fifo$13.$group_7'.
  created $dff cell `$procdff$156' with positive edge clock.
Creating register for signal `\fifo$13.\level' using process `\fifo$13.$group_11'.
  created $dff cell `$procdff$157' with positive edge clock.
Creating register for signal `\trascon$11.\ready' using process `\trascon$11.$group_1'.
  created $dff cell `$procdff$158' with positive edge clock.
Creating register for signal `\trascon$11.\count' using process `\trascon$11.$group_0'.
  created $dff cell `$procdff$159' with positive edge clock.
Creating register for signal `\trccon$10.\ready' using process `\trccon$10.$group_1'.
  created $dff cell `$procdff$160' with positive edge clock.
Creating register for signal `\trccon$10.\count' using process `\trccon$10.$group_0'.
  created $dff cell `$procdff$161' with positive edge clock.
Creating register for signal `\twtpcon$9.\ready' using process `\twtpcon$9.$group_1'.
  created $dff cell `$procdff$162' with positive edge clock.
Creating register for signal `\twtpcon$9.\count' using process `\twtpcon$9.$group_0'.
  created $dff cell `$procdff$163' with positive edge clock.
Creating register for signal `\bankmachine0.\row' using process `\bankmachine0.$group_16'.
  created $dff cell `$procdff$164' with positive edge clock.
Creating register for signal `\bankmachine0.\row_opened' using process `\bankmachine0.$group_15'.
  created $dff cell `$procdff$165' with positive edge clock.
Creating register for signal `\bankmachine0.\fsm_state' using process `\bankmachine0.$group_24'.
  created $dff cell `$procdff$166' with positive edge clock.
Creating register for signal `\U$$1$6.\source__payload__we' using process `\U$$1$6.$group_3'.
  created $dff cell `$procdff$167' with positive edge clock.
Creating register for signal `\U$$1$6.\source__payload__addr' using process `\U$$1$6.$group_3'.
  created $dff cell `$procdff$168' with positive edge clock.
Creating register for signal `\U$$1$6.\source__last' using process `\U$$1$6.$group_2'.
  created $dff cell `$procdff$169' with positive edge clock.
Creating register for signal `\U$$1$6.\source__first' using process `\U$$1$6.$group_1'.
  created $dff cell `$procdff$170' with positive edge clock.
Creating register for signal `\U$$1$6.\source__valid' using process `\U$$1$6.$group_0'.
  created $dff cell `$procdff$171' with positive edge clock.
Creating register for signal `\fifo.\consume' using process `\fifo.$group_10'.
  created $dff cell `$procdff$172' with positive edge clock.
Creating register for signal `\fifo.\produce' using process `\fifo.$group_7'.
  created $dff cell `$procdff$173' with positive edge clock.
Creating register for signal `\fifo.\level' using process `\fifo.$group_11'.
  created $dff cell `$procdff$174' with positive edge clock.
Creating register for signal `\trascon.\ready' using process `\trascon.$group_1'.
  created $dff cell `$procdff$175' with positive edge clock.
Creating register for signal `\trascon.\count' using process `\trascon.$group_0'.
  created $dff cell `$procdff$176' with positive edge clock.
Creating register for signal `\trccon.\ready' using process `\trccon.$group_1'.
  created $dff cell `$procdff$177' with positive edge clock.
Creating register for signal `\trccon.\count' using process `\trccon.$group_0'.
  created $dff cell `$procdff$178' with positive edge clock.
Creating register for signal `\twtpcon.\ready' using process `\twtpcon.$group_1'.
  created $dff cell `$procdff$179' with positive edge clock.
Creating register for signal `\twtpcon.\count' using process `\twtpcon.$group_0'.
  created $dff cell `$procdff$180' with positive edge clock.
Creating register for signal `\refresher.\fsm_state' using process `\refresher.$group_4'.
  created $dff cell `$procdff$181' with positive edge clock.
Creating register for signal `\timeline$5.\done' using process `\timeline$5.$group_6'.
  created $dff cell `$procdff$182' with positive edge clock.
Creating register for signal `\timeline$5.\we' using process `\timeline$5.$group_5'.
  created $dff cell `$procdff$183' with positive edge clock.
Creating register for signal `\timeline$5.\ras' using process `\timeline$5.$group_4'.
  created $dff cell `$procdff$184' with positive edge clock.
Creating register for signal `\timeline$5.\cas' using process `\timeline$5.$group_3'.
  created $dff cell `$procdff$185' with positive edge clock.
Creating register for signal `\timeline$5.\ba' using process `\timeline$5.$group_2'.
  created $dff cell `$procdff$186' with positive edge clock.
Creating register for signal `\timeline$5.\a' using process `\timeline$5.$group_1'.
  created $dff cell `$procdff$187' with positive edge clock.
Creating register for signal `\timeline$5.\counter' using process `\timeline$5.$group_0'.
  created $dff cell `$procdff$188' with positive edge clock.
Creating register for signal `\zqcs_timer.\done' using process `\zqcs_timer.$group_1'.
  created $dff cell `$procdff$189' with positive edge clock.
Creating register for signal `\zqcs_timer.\count' using process `\zqcs_timer.$group_0'.
  created $dff cell `$procdff$190' with positive edge clock.
Creating register for signal `\sequencer.\count' using process `\sequencer.$group_5'.
  created $dff cell `$procdff$191' with positive edge clock.
Creating register for signal `\sequencer.\countDiffZero' using process `\sequencer.$group_7'.
  created $dff cell `$procdff$192' with positive edge clock.
Creating register for signal `\sequencer.\countEqZero' using process `\sequencer.$group_6'.
  created $dff cell `$procdff$193' with positive edge clock.
Creating register for signal `\timeline.\done' using process `\timeline.$group_6'.
  created $dff cell `$procdff$194' with positive edge clock.
Creating register for signal `\timeline.\we' using process `\timeline.$group_5'.
  created $dff cell `$procdff$195' with positive edge clock.
Creating register for signal `\timeline.\ras' using process `\timeline.$group_4'.
  created $dff cell `$procdff$196' with positive edge clock.
Creating register for signal `\timeline.\cas' using process `\timeline.$group_3'.
  created $dff cell `$procdff$197' with positive edge clock.
Creating register for signal `\timeline.\ba' using process `\timeline.$group_2'.
  created $dff cell `$procdff$198' with positive edge clock.
Creating register for signal `\timeline.\a' using process `\timeline.$group_1'.
  created $dff cell `$procdff$199' with positive edge clock.
Creating register for signal `\timeline.\counter' using process `\timeline.$group_0'.
  created $dff cell `$procdff$200' with positive edge clock.
Creating register for signal `\postponer.\req_o' using process `\postponer.$group_1'.
  created $dff cell `$procdff$201' with positive edge clock.
Creating register for signal `\postponer.\count' using process `\postponer.$group_0'.
  created $dff cell `$procdff$202' with positive edge clock.
Creating register for signal `\timer.\done' using process `\timer.$group_1'.
  created $dff cell `$procdff$203' with positive edge clock.
Creating register for signal `\timer.\count' using process `\timer.$group_0'.
  created $dff cell `$procdff$204' with positive edge clock.
Creating register for signal `\phase_1.\dfii_p1_rddata__r_data' using process `\phase_1.$group_10'.
  created $dff cell `$procdff$205' with positive edge clock.
Creating register for signal `\phase_0.\dfii_p0_rddata__r_data' using process `\phase_0.$group_10'.
  created $dff cell `$procdff$206' with positive edge clock.
Creating register for signal `\csr_bridge_0$3.\cycle' using process `\csr_bridge_0$3.$group_5'.
  created $dff cell `$procdff$207' with positive edge clock.
Creating register for signal `\csr_bridge_0$3.\wb__ack' using process `\csr_bridge_0$3.$group_7'.
  created $dff cell `$procdff$208' with positive edge clock.
Creating register for signal `\csr_bridge_0$3.\wb__dat_r' using process `\csr_bridge_0$3.$group_6'.
  created $dff cell `$procdff$209' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p1_rddata__shadow_en' using process `\csr_mux_0$2.$group_36'.
  created $dff cell `$procdff$210' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p1_command_issue__shadow' using process `\csr_mux_0$2.$group_26'.
  created $dff cell `$procdff$211' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p1_command_issue__w_stb' using process `\csr_mux_0$2.$group_25'.
  created $dff cell `$procdff$212' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p1_wrdata__shadow' using process `\csr_mux_0$2.$group_35'.
  created $dff cell `$procdff$213' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p1_command__shadow' using process `\csr_mux_0$2.$group_23'.
  created $dff cell `$procdff$214' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p1_command__w_stb' using process `\csr_mux_0$2.$group_22'.
  created $dff cell `$procdff$215' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p1_wrdata__w_stb' using process `\csr_mux_0$2.$group_34'.
  created $dff cell `$procdff$216' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p0_rddata__shadow' using process `\csr_mux_0$2.$group_20'.
  created $dff cell `$procdff$217' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p0_rddata__shadow_en' using process `\csr_mux_0$2.$group_18'.
  created $dff cell `$procdff$218' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p0_wrdata__shadow' using process `\csr_mux_0$2.$group_17'.
  created $dff cell `$procdff$219' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p0_wrdata__w_stb' using process `\csr_mux_0$2.$group_16'.
  created $dff cell `$procdff$220' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p1_rddata__shadow' using process `\csr_mux_0$2.$group_38'.
  created $dff cell `$procdff$221' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p0_baddress__shadow' using process `\csr_mux_0$2.$group_14'.
  created $dff cell `$procdff$222' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p0_baddress__w_stb' using process `\csr_mux_0$2.$group_13'.
  created $dff cell `$procdff$223' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p1_baddress__shadow' using process `\csr_mux_0$2.$group_32'.
  created $dff cell `$procdff$224' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p0_address__shadow' using process `\csr_mux_0$2.$group_11'.
  created $dff cell `$procdff$225' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p0_address__w_stb' using process `\csr_mux_0$2.$group_10'.
  created $dff cell `$procdff$226' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p1_baddress__w_stb' using process `\csr_mux_0$2.$group_31'.
  created $dff cell `$procdff$227' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p0_command_issue__shadow' using process `\csr_mux_0$2.$group_8'.
  created $dff cell `$procdff$228' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p0_command_issue__w_stb' using process `\csr_mux_0$2.$group_7'.
  created $dff cell `$procdff$229' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p0_command__shadow' using process `\csr_mux_0$2.$group_5'.
  created $dff cell `$procdff$230' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p0_command__w_stb' using process `\csr_mux_0$2.$group_4'.
  created $dff cell `$procdff$231' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p1_address__shadow' using process `\csr_mux_0$2.$group_29'.
  created $dff cell `$procdff$232' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_control__shadow' using process `\csr_mux_0$2.$group_2'.
  created $dff cell `$procdff$233' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_control__w_stb' using process `\csr_mux_0$2.$group_1'.
  created $dff cell `$procdff$234' with positive edge clock.
Creating register for signal `\csr_mux_0$2.\dfii_p1_address__w_stb' using process `\csr_mux_0$2.$group_28'.
  created $dff cell `$procdff$235' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d$373' using process `\ddrphy.$group_122'.
  created $dff cell `$procdff$236' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed$48' using process `\ddrphy.$group_89'.
  created $dff cell `$procdff$237' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d$351' using process `\ddrphy.$group_88'.
  created $dff cell `$procdff$238' with positive edge clock.
Creating register for signal `\ddrphy.\wrdata_en_last' using process `\ddrphy.$group_139'.
  created $dff cell `$procdff$239' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed$38' using process `\ddrphy.$group_86'.
  created $dff cell `$procdff$240' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d$349' using process `\ddrphy.$group_85'.
  created $dff cell `$procdff$241' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed$159' using process `\ddrphy.$group_120'.
  created $dff cell `$procdff$242' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed$28' using process `\ddrphy.$group_83'.
  created $dff cell `$procdff$243' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d$347' using process `\ddrphy.$group_82'.
  created $dff cell `$procdff$244' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d$371' using process `\ddrphy.$group_119'.
  created $dff cell `$procdff$245' with positive edge clock.
Creating register for signal `\ddrphy.\ecp5phy__rddata$12' using process `\ddrphy.$group_80'.
  created $dff cell `$procdff$246' with positive edge clock.
Creating register for signal `\ddrphy.\ecp5phy__rddata' using process `\ddrphy.$group_79'.
  created $dff cell `$procdff$247' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed' using process `\ddrphy.$group_78'.
  created $dff cell `$procdff$248' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d' using process `\ddrphy.$group_77'.
  created $dff cell `$procdff$249' with positive edge clock.
Creating register for signal `\ddrphy.\rddata_en_last' using process `\ddrphy.$group_131'.
  created $dff cell `$procdff$250' with positive edge clock.
Creating register for signal `\ddrphy.\dm_o_data_muxed' using process `\ddrphy.$group_75'.
  created $dff cell `$procdff$251' with positive edge clock.
Creating register for signal `\ddrphy.\dm_o_data_d' using process `\ddrphy.$group_74'.
  created $dff cell `$procdff$252' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed$149' using process `\ddrphy.$group_117'.
  created $dff cell `$procdff$253' with positive edge clock.
Creating register for signal `\ddrphy.\datavalid_prev' using process `\ddrphy.$group_72'.
  created $dff cell `$procdff$254' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d$369' using process `\ddrphy.$group_116'.
  created $dff cell `$procdff$255' with positive edge clock.
Creating register for signal `\ddrphy.$sample$s$burstdet$sync$1' using process `\ddrphy.$group_145'.
  created $dff cell `$procdff$256' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed$139' using process `\ddrphy.$group_114'.
  created $dff cell `$procdff$257' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d$367' using process `\ddrphy.$group_113'.
  created $dff cell `$procdff$258' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed$189' using process `\ddrphy.$group_129'.
  created $dff cell `$procdff$259' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed$129' using process `\ddrphy.$group_111'.
  created $dff cell `$procdff$260' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d$365' using process `\ddrphy.$group_110'.
  created $dff cell `$procdff$261' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d$377' using process `\ddrphy.$group_128'.
  created $dff cell `$procdff$262' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed$119' using process `\ddrphy.$group_108'.
  created $dff cell `$procdff$263' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d$363' using process `\ddrphy.$group_107'.
  created $dff cell `$procdff$264' with positive edge clock.
Creating register for signal `\ddrphy.$sample$s$burstdet$sync$1$204' using process `\ddrphy.$group_146'.
  created $dff cell `$procdff$265' with positive edge clock.
Creating register for signal `\ddrphy.\dm_o_data_muxed$108' using process `\ddrphy.$group_105'.
  created $dff cell `$procdff$266' with positive edge clock.
Creating register for signal `\ddrphy.\dm_o_data_d$361' using process `\ddrphy.$group_104'.
  created $dff cell `$procdff$267' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed$179' using process `\ddrphy.$group_126'.
  created $dff cell `$procdff$268' with positive edge clock.
Creating register for signal `\ddrphy.\datavalid_prev$250' using process `\ddrphy.$group_102'.
  created $dff cell `$procdff$269' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed$88' using process `\ddrphy.$group_101'.
  created $dff cell `$procdff$270' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d$359' using process `\ddrphy.$group_100'.
  created $dff cell `$procdff$271' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d$375' using process `\ddrphy.$group_125'.
  created $dff cell `$procdff$272' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed$78' using process `\ddrphy.$group_98'.
  created $dff cell `$procdff$273' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d$357' using process `\ddrphy.$group_97'.
  created $dff cell `$procdff$274' with positive edge clock.
Creating register for signal `\ddrphy.\rddata_valid' using process `\ddrphy.$group_133'.
  created $dff cell `$procdff$275' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed$68' using process `\ddrphy.$group_95'.
  created $dff cell `$procdff$276' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d$355' using process `\ddrphy.$group_94'.
  created $dff cell `$procdff$277' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed$169' using process `\ddrphy.$group_123'.
  created $dff cell `$procdff$278' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_muxed$58' using process `\ddrphy.$group_92'.
  created $dff cell `$procdff$279' with positive edge clock.
Creating register for signal `\ddrphy.\burstdet_reg' using process `\ddrphy.$group_1'.
  created $dff cell `$procdff$280' with positive edge clock.
Creating register for signal `\ddrphy.\dq_o_data_d$353' using process `\ddrphy.$group_91'.
  created $dff cell `$procdff$281' with positive edge clock.
Creating register for signal `\dqsbufm_manager1.\readclksel' using process `\dqsbufm_manager1.$group_2'.
  created $dff cell `$procdff$282' with positive edge clock.
Creating register for signal `\dqsbufm_manager1.\fsm_state' using process `\dqsbufm_manager1.$group_1'.
  created $dff cell `$procdff$283' with positive edge clock.
Creating register for signal `\dqsbufm_manager1.\pause' using process `\dqsbufm_manager1.$group_0'.
  created $dff cell `$procdff$284' with positive edge clock.
Creating register for signal `\dqsbufm_manager0.\readclksel' using process `\dqsbufm_manager0.$group_2'.
  created $dff cell `$procdff$285' with positive edge clock.
Creating register for signal `\dqsbufm_manager0.\fsm_state' using process `\dqsbufm_manager0.$group_1'.
  created $dff cell `$procdff$286' with positive edge clock.
Creating register for signal `\dqsbufm_manager0.\pause' using process `\dqsbufm_manager0.$group_0'.
  created $dff cell `$procdff$287' with positive edge clock.
Creating register for signal `\init.\lock_d' using process `\init.$group_0'.
  created $dff cell `$procdff$288' with positive edge clock.
Creating register for signal `\U$$2.\update' using process `\U$$2.$group_5'.
  created $dff cell `$procdff$289' with positive edge clock.
Creating register for signal `\U$$2.\pause' using process `\U$$2.$group_4'.
  created $dff cell `$procdff$290' with positive edge clock.
Creating register for signal `\U$$2.\reset' using process `\U$$2.$group_3'.
  created $dff cell `$procdff$291' with positive edge clock.
Creating register for signal `\U$$2.\stop' using process `\U$$2.$group_2'.
  created $dff cell `$procdff$292' with positive edge clock.
Creating register for signal `\U$$2.\freeze' using process `\U$$2.$group_1'.
  created $dff cell `$procdff$293' with positive edge clock.
Creating register for signal `\U$$2.\counter' using process `\U$$2.$group_0'.
  created $dff cell `$procdff$294' with positive edge clock.
Creating register for signal `\U$$1.\stage1' using process `\U$$1.$group_1'.
  created $dff cell `$procdff$295' with positive edge clock.
Creating register for signal `\U$$1.\stage0' using process `\U$$1.$group_0'.
  created $dff cell `$procdff$296' with positive edge clock.
Creating register for signal `\csr_bridge_0.\cycle' using process `\csr_bridge_0.$group_5'.
  created $dff cell `$procdff$297' with positive edge clock.
Creating register for signal `\csr_bridge_0.\wb__ack' using process `\csr_bridge_0.$group_7'.
  created $dff cell `$procdff$298' with positive edge clock.
Creating register for signal `\csr_bridge_0.\wb__dat_r' using process `\csr_bridge_0.$group_6'.
  created $dff cell `$procdff$299' with positive edge clock.
Creating register for signal `\csr_mux_0.\bitslip__shadow_en' using process `\csr_mux_0.$group_15'.
  created $dff cell `$procdff$300' with positive edge clock.
Creating register for signal `\csr_mux_0.\rdly_p1__shadow' using process `\csr_mux_0.$group_14'.
  created $dff cell `$procdff$301' with positive edge clock.
Creating register for signal `\csr_mux_0.\rdly_p1__w_stb' using process `\csr_mux_0.$group_12'.
  created $dff cell `$procdff$302' with positive edge clock.
Creating register for signal `\csr_mux_0.\rdly_p1__shadow_en' using process `\csr_mux_0.$group_10'.
  created $dff cell `$procdff$303' with positive edge clock.
Creating register for signal `\csr_mux_0.\rdly_p0__shadow' using process `\csr_mux_0.$group_9'.
  created $dff cell `$procdff$304' with positive edge clock.
Creating register for signal `\csr_mux_0.\rdly_p0__w_stb' using process `\csr_mux_0.$group_7'.
  created $dff cell `$procdff$305' with positive edge clock.
Creating register for signal `\csr_mux_0.\bitslip__w_stb' using process `\csr_mux_0.$group_17'.
  created $dff cell `$procdff$306' with positive edge clock.
Creating register for signal `\csr_mux_0.\rdly_p0__shadow_en' using process `\csr_mux_0.$group_5'.
  created $dff cell `$procdff$307' with positive edge clock.
Creating register for signal `\csr_mux_0.\burstdet__shadow' using process `\csr_mux_0.$group_4'.
  created $dff cell `$procdff$308' with positive edge clock.
Creating register for signal `\csr_mux_0.\burstdet__w_stb' using process `\csr_mux_0.$group_2'.
  created $dff cell `$procdff$309' with positive edge clock.
Creating register for signal `\csr_mux_0.\bitslip__shadow' using process `\csr_mux_0.$group_19'.
  created $dff cell `$procdff$310' with positive edge clock.
Creating register for signal `\csr_mux_0.\burstdet__shadow_en' using process `\csr_mux_0.$group_0'.
  created $dff cell `$procdff$311' with positive edge clock.
Creating register for signal `\sysclk.\podcnt' using process `\sysclk.$group_1'.
  created $dff cell `$procdff$312' with positive edge clock.
Creating register for signal `\sysclk.\pod_done' using process `\sysclk.$group_2'.
  created $dff cell `$procdff$313' with positive edge clock.

9. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\drambone.$group_8'.
     1/1: \cmd__payload__addr
Creating decoders for process `\drambone.$group_7'.
     1/1: \cmd__payload__we
Creating decoders for process `\drambone.$group_6'.
     1/1: \cmd__valid
Creating decoders for process `\drambone.$group_5'.
     1/1: \bus__dat_r
Creating decoders for process `\drambone.$group_10'.
     1/1: \bus__ack
Creating decoders for process `\drambone.$group_3'.
     1/1: \wdata__payload__data
Creating decoders for process `\drambone.$group_2'.
     1/1: \wdata__payload__we
Creating decoders for process `\drambone.$group_1'.
     1/1: \sel
Creating decoders for process `\drambone.$group_9'.
     1/1: \fsm_state$next
Creating decoders for process `\crossbar.$group_39'.
     1/1: \wdata_we
Creating decoders for process `\crossbar.$group_24'.
     1/1: \bank5__valid
Creating decoders for process `\crossbar.$group_23'.
     1/1: \bank5__we
Creating decoders for process `\crossbar.$group_22'.
     1/1: \bank5__addr
Creating decoders for process `\crossbar.$group_32'.
     1/1: \bank7__valid
Creating decoders for process `\crossbar.$group_20'.
     1/1: \bank4__valid
Creating decoders for process `\crossbar.$group_19'.
     1/1: \bank4__we
Creating decoders for process `\crossbar.$group_18'.
     1/1: \bank4__addr
Creating decoders for process `\crossbar.$group_31'.
     1/1: \bank7__we
Creating decoders for process `\crossbar.$group_16'.
     1/1: \bank3__valid
Creating decoders for process `\crossbar.$group_15'.
     1/1: \bank3__we
Creating decoders for process `\crossbar.$group_14'.
     1/1: \bank3__addr
Creating decoders for process `\crossbar.$group_30'.
     1/1: \bank7__addr
Creating decoders for process `\crossbar.$group_12'.
     1/1: \bank2__valid
Creating decoders for process `\crossbar.$group_11'.
     1/1: \bank2__we
Creating decoders for process `\crossbar.$group_10'.
     1/1: \bank2__addr
Creating decoders for process `\crossbar.$group_38'.
     1/1: \wdata
Creating decoders for process `\crossbar.$group_8'.
     1/1: \bank1__valid
Creating decoders for process `\crossbar.$group_7'.
     1/1: \bank1__we
Creating decoders for process `\crossbar.$group_6'.
     1/1: \bank1__addr
Creating decoders for process `\crossbar.$group_28'.
     1/1: \bank6__valid
Creating decoders for process `\crossbar.$group_4'.
     1/1: \bank0__valid
Creating decoders for process `\crossbar.$group_3'.
     1/1: \bank0__we
Creating decoders for process `\crossbar.$group_2'.
     1/1: \bank0__addr
Creating decoders for process `\crossbar.$group_27'.
     1/1: \bank6__we
Creating decoders for process `\crossbar.$group_26'.
     1/1: \bank6__addr
Creating decoders for process `\U$$9.$group_0'.
     1/1: \buffer$next
Creating decoders for process `\U$$8.$group_0'.
     1/1: \buffer$next
Creating decoders for process `\U$$7.$group_0'.
     1/1: \valid$next
Creating decoders for process `\U$$6.$group_0'.
     1/1: \valid$next
Creating decoders for process `\U$$5.$group_0'.
     1/1: \valid$next
Creating decoders for process `\U$$4.$group_0'.
     1/1: \valid$next
Creating decoders for process `\U$$3.$group_0'.
     1/1: \valid$next
Creating decoders for process `\U$$2$66.$group_0'.
     1/1: \valid$next
Creating decoders for process `\U$$1$65.$group_0'.
     1/1: \valid$next
Creating decoders for process `\U$$0$64.$group_0'.
     1/1: \valid$next
Creating decoders for process `\multiplexer.$group_34'.
     1/1: \choose_req_cmd__ready
Creating decoders for process `\multiplexer.$group_33'.
     1/1: \steerer_$signal$106
Creating decoders for process `\multiplexer.$group_32'.
     1/1: \steerer_$signal
Creating decoders for process `\multiplexer.$group_31'.
     1/1: \choose_req_want_reads
Creating decoders for process `\multiplexer.$group_30'.
     1/1: \read_antistarvation_en
Creating decoders for process `\multiplexer.$group_40'.
     1/1: \cmd__ready
Creating decoders for process `\multiplexer.$group_39'.
     1/1: \choose_req_want_writes
Creating decoders for process `\multiplexer.$group_38'.
     1/1: \write_antistarvation_en
Creating decoders for process `\multiplexer.$group_37'.
     1/1: \fsm_state$next
Creating decoders for process `\multiplexer.$group_36'.
     1/1: \choose_cmd_cmd__ready
Creating decoders for process `\multiplexer.$group_35'.
     1/1: \choose_cmd_want_activates
Creating decoders for process `\write_antistarvation.$group_1'.
     1/1: \max_time$next
Creating decoders for process `\write_antistarvation.$group_0'.
     1/1: \time$next
Creating decoders for process `\read_antistarvation.$group_1'.
     1/1: \max_time$next
Creating decoders for process `\read_antistarvation.$group_0'.
     1/1: \time$next
Creating decoders for process `\twtrcon.$group_1'.
     1/1: \ready$next
Creating decoders for process `\twtrcon.$group_0'.
     1/1: \count$next
Creating decoders for process `\tccdcon.$group_1'.
     1/1: \ready$next
Creating decoders for process `\tccdcon.$group_0'.
     1/1: \count$next
Creating decoders for process `\tfawcon.$group_2'.
     1/1: \ready$next
Creating decoders for process `\tfawcon.$group_0'.
     1/1: \window$next
Creating decoders for process `\trrdcon.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trrdcon.$group_0'.
     1/1: \count$next
Creating decoders for process `\steerer.$group_15'.
     1/1: \mem_dfi__bank$2$next
Creating decoders for process `\steerer.$group_14'.
     1/1: \mem_dfi__cs_n$4$next
Creating decoders for process `\steerer.$group_21'.
     1/1: \mem_dfi__wrdata_en$10$next
Creating decoders for process `\steerer.$group_20'.
     1/1: \mem_dfi__rddata_en$11$next
Creating decoders for process `\steerer.$group_19'.
     1/1: \mem_dfi__we$6$next
Creating decoders for process `\steerer.$group_10'.
     1/1: \mem_dfi__wrdata_en$next
Creating decoders for process `\steerer.$group_9'.
     1/1: \mem_dfi__rddata_en$next
Creating decoders for process `\steerer.$group_8'.
     1/1: \mem_dfi__we$next
Creating decoders for process `\steerer.$group_7'.
     1/1: \mem_dfi__ras$next
Creating decoders for process `\steerer.$group_6'.
     1/1: \mem_dfi__cas$next
Creating decoders for process `\steerer.$group_5'.
     1/1: \mem_dfi__address$next
Creating decoders for process `\steerer.$group_4'.
     1/1: \mem_dfi__bank$next
Creating decoders for process `\steerer.$group_3'.
     1/1: \mem_dfi__cs_n$next
Creating decoders for process `\steerer.$group_18'.
     1/1: \mem_dfi__ras$5$next
Creating decoders for process `\steerer.$group_17'.
     1/1: \mem_dfi__cas$3$next
Creating decoders for process `\steerer.$group_16'.
     1/1: \mem_dfi__address$1$next
Creating decoders for process `\choose_req.$group_9'.
     1/1: \cmd__payload__ras$67
Creating decoders for process `\choose_req.$group_8'.
     1/1: \cmd__payload__cas$68
Creating decoders for process `\choose_req.$group_7'.
     1/1: \cmd__payload__is_cmd$280
Creating decoders for process `\choose_req.$group_6'.
     1/1: \cmd__payload__is_write$65
Creating decoders for process `\choose_req.$group_5'.
     1/1: \cmd__payload__is_read$66
Creating decoders for process `\choose_req.$group_4'.
     1/1: \cmd__payload__ba$71
Creating decoders for process `\choose_req.$group_3'.
     1/1: \cmd__payload__a$70
Creating decoders for process `\choose_req.$group_2'.
     1/1: \cmd__valid$64
Creating decoders for process `\choose_req.$group_11'.
     1/8: \ready [7]
     2/8: \ready [6]
     3/8: \ready [5]
     4/8: \ready [4]
     5/8: \ready [3]
     6/8: \ready [2]
     7/8: \ready [1]
     8/8: \ready [0]
Creating decoders for process `\choose_req.$group_10'.
     1/1: \cmd__payload__we$69
Creating decoders for process `\arbiter$63.$group_1'.
     1/1: \valid$next
Creating decoders for process `\arbiter$63.$group_0'.
     1/1: \grant$next
Creating decoders for process `\choose_cmd.$group_9'.
     1/1: \cmd__payload__ras$65
Creating decoders for process `\choose_cmd.$group_8'.
     1/1: \cmd__payload__cas$66
Creating decoders for process `\choose_cmd.$group_7'.
     1/1: \cmd__payload__is_cmd$280
Creating decoders for process `\choose_cmd.$group_6'.
     1/1: \cmd__payload__is_write$71
Creating decoders for process `\choose_cmd.$group_5'.
     1/1: \cmd__payload__is_read$70
Creating decoders for process `\choose_cmd.$group_4'.
     1/1: \cmd__payload__ba$69
Creating decoders for process `\choose_cmd.$group_3'.
     1/1: \cmd__payload__a$68
Creating decoders for process `\choose_cmd.$group_2'.
     1/1: \cmd__valid$64
Creating decoders for process `\choose_cmd.$group_11'.
     1/8: \ready [7]
     2/8: \ready [6]
     3/8: \ready [5]
     4/8: \ready [4]
     5/8: \ready [3]
     6/8: \ready [2]
     7/8: \ready [1]
     8/8: \ready [0]
Creating decoders for process `\choose_cmd.$group_10'.
     1/1: \cmd__payload__we$67
Creating decoders for process `\arbiter.$group_1'.
     1/1: \valid$next
Creating decoders for process `\arbiter.$group_0'.
     1/1: \grant$next
Creating decoders for process `\bankmachine7.$group_33'.
     1/1: \cmd__payload__ras
Creating decoders for process `\bankmachine7.$group_16'.
     1/1: \row$next
Creating decoders for process `\bankmachine7.$group_15'.
     1/1: \row_opened$next
Creating decoders for process `\bankmachine7.$group_32'.
     1/1: \row_close
Creating decoders for process `\bankmachine7.$group_31'.
     1/1: \cmd__payload__is_read
Creating decoders for process `\bankmachine7.$group_30'.
     1/1: \req__rdata_valid
Creating decoders for process `\bankmachine7.$group_29'.
     1/1: \cmd__payload__we
Creating decoders for process `\bankmachine7.$group_28'.
     1/1: \cmd__payload__is_write
Creating decoders for process `\bankmachine7.$group_27'.
     1/1: \req__wdata_ready
Creating decoders for process `\bankmachine7.$group_26'.
     1/1: \cmd__payload__cas
Creating decoders for process `\bankmachine7.$group_25'.
     1/1: \cmd__valid
Creating decoders for process `\bankmachine7.$group_24'.
     1/1: \fsm_state$next
Creating decoders for process `\bankmachine7.$group_23'.
     1/1: \auto_precharge
Creating decoders for process `\bankmachine7.$group_37'.
     1/1: \refresh_gnt
Creating decoders for process `\bankmachine7.$group_36'.
     1/1: \row_open
Creating decoders for process `\bankmachine7.$group_35'.
     1/1: \row_col_n_addr_sel
Creating decoders for process `\bankmachine7.$group_34'.
     1/1: \cmd__payload__is_cmd
Creating decoders for process `\bankmachine7.$group_18'.
     1/1: \cmd__payload__a
Creating decoders for process `\U$$1$62.$group_3'.
     1/2: \source__payload__addr$next
     2/2: \source__payload__we$next
Creating decoders for process `\U$$1$62.$group_2'.
     1/1: \source__last$next
Creating decoders for process `\U$$1$62.$group_1'.
     1/1: \source__first$next
Creating decoders for process `\U$$1$62.$group_0'.
     1/1: \source__valid$next
Creating decoders for process `\fifo$61.$group_10'.
     1/1: \consume$next
Creating decoders for process `\fifo$61.$group_7'.
     1/1: \produce$next
Creating decoders for process `\fifo$61.$group_11'.
     1/1: \level$next
Creating decoders for process `\trascon$59.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trascon$59.$group_0'.
     1/1: \count$next
Creating decoders for process `\trccon$58.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trccon$58.$group_0'.
     1/1: \count$next
Creating decoders for process `\twtpcon$57.$group_1'.
     1/1: \ready$next
Creating decoders for process `\twtpcon$57.$group_0'.
     1/1: \count$next
Creating decoders for process `\bankmachine6.$group_33'.
     1/1: \cmd__payload__ras
Creating decoders for process `\bankmachine6.$group_16'.
     1/1: \row$next
Creating decoders for process `\bankmachine6.$group_15'.
     1/1: \row_opened$next
Creating decoders for process `\bankmachine6.$group_32'.
     1/1: \row_close
Creating decoders for process `\bankmachine6.$group_31'.
     1/1: \cmd__payload__is_read
Creating decoders for process `\bankmachine6.$group_30'.
     1/1: \req__rdata_valid
Creating decoders for process `\bankmachine6.$group_29'.
     1/1: \cmd__payload__we
Creating decoders for process `\bankmachine6.$group_28'.
     1/1: \cmd__payload__is_write
Creating decoders for process `\bankmachine6.$group_27'.
     1/1: \req__wdata_ready
Creating decoders for process `\bankmachine6.$group_26'.
     1/1: \cmd__payload__cas
Creating decoders for process `\bankmachine6.$group_25'.
     1/1: \cmd__valid
Creating decoders for process `\bankmachine6.$group_24'.
     1/1: \fsm_state$next
Creating decoders for process `\bankmachine6.$group_23'.
     1/1: \auto_precharge
Creating decoders for process `\bankmachine6.$group_37'.
     1/1: \refresh_gnt
Creating decoders for process `\bankmachine6.$group_36'.
     1/1: \row_open
Creating decoders for process `\bankmachine6.$group_35'.
     1/1: \row_col_n_addr_sel
Creating decoders for process `\bankmachine6.$group_34'.
     1/1: \cmd__payload__is_cmd
Creating decoders for process `\bankmachine6.$group_18'.
     1/1: \cmd__payload__a
Creating decoders for process `\U$$1$54.$group_3'.
     1/2: \source__payload__addr$next
     2/2: \source__payload__we$next
Creating decoders for process `\U$$1$54.$group_2'.
     1/1: \source__last$next
Creating decoders for process `\U$$1$54.$group_1'.
     1/1: \source__first$next
Creating decoders for process `\U$$1$54.$group_0'.
     1/1: \source__valid$next
Creating decoders for process `\fifo$53.$group_10'.
     1/1: \consume$next
Creating decoders for process `\fifo$53.$group_7'.
     1/1: \produce$next
Creating decoders for process `\fifo$53.$group_11'.
     1/1: \level$next
Creating decoders for process `\trascon$51.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trascon$51.$group_0'.
     1/1: \count$next
Creating decoders for process `\trccon$50.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trccon$50.$group_0'.
     1/1: \count$next
Creating decoders for process `\twtpcon$49.$group_1'.
     1/1: \ready$next
Creating decoders for process `\twtpcon$49.$group_0'.
     1/1: \count$next
Creating decoders for process `\bankmachine5.$group_33'.
     1/1: \cmd__payload__ras
Creating decoders for process `\bankmachine5.$group_16'.
     1/1: \row$next
Creating decoders for process `\bankmachine5.$group_15'.
     1/1: \row_opened$next
Creating decoders for process `\bankmachine5.$group_32'.
     1/1: \row_close
Creating decoders for process `\bankmachine5.$group_31'.
     1/1: \cmd__payload__is_read
Creating decoders for process `\bankmachine5.$group_30'.
     1/1: \req__rdata_valid
Creating decoders for process `\bankmachine5.$group_29'.
     1/1: \cmd__payload__we
Creating decoders for process `\bankmachine5.$group_28'.
     1/1: \cmd__payload__is_write
Creating decoders for process `\bankmachine5.$group_27'.
     1/1: \req__wdata_ready
Creating decoders for process `\bankmachine5.$group_26'.
     1/1: \cmd__payload__cas
Creating decoders for process `\bankmachine5.$group_25'.
     1/1: \cmd__valid
Creating decoders for process `\bankmachine5.$group_24'.
     1/1: \fsm_state$next
Creating decoders for process `\bankmachine5.$group_23'.
     1/1: \auto_precharge
Creating decoders for process `\bankmachine5.$group_37'.
     1/1: \refresh_gnt
Creating decoders for process `\bankmachine5.$group_36'.
     1/1: \row_open
Creating decoders for process `\bankmachine5.$group_35'.
     1/1: \row_col_n_addr_sel
Creating decoders for process `\bankmachine5.$group_34'.
     1/1: \cmd__payload__is_cmd
Creating decoders for process `\bankmachine5.$group_18'.
     1/1: \cmd__payload__a
Creating decoders for process `\U$$1$46.$group_3'.
     1/2: \source__payload__addr$next
     2/2: \source__payload__we$next
Creating decoders for process `\U$$1$46.$group_2'.
     1/1: \source__last$next
Creating decoders for process `\U$$1$46.$group_1'.
     1/1: \source__first$next
Creating decoders for process `\U$$1$46.$group_0'.
     1/1: \source__valid$next
Creating decoders for process `\fifo$45.$group_10'.
     1/1: \consume$next
Creating decoders for process `\fifo$45.$group_7'.
     1/1: \produce$next
Creating decoders for process `\fifo$45.$group_11'.
     1/1: \level$next
Creating decoders for process `\trascon$43.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trascon$43.$group_0'.
     1/1: \count$next
Creating decoders for process `\trccon$42.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trccon$42.$group_0'.
     1/1: \count$next
Creating decoders for process `\twtpcon$41.$group_1'.
     1/1: \ready$next
Creating decoders for process `\twtpcon$41.$group_0'.
     1/1: \count$next
Creating decoders for process `\bankmachine4.$group_33'.
     1/1: \cmd__payload__ras
Creating decoders for process `\bankmachine4.$group_16'.
     1/1: \row$next
Creating decoders for process `\bankmachine4.$group_15'.
     1/1: \row_opened$next
Creating decoders for process `\bankmachine4.$group_32'.
     1/1: \row_close
Creating decoders for process `\bankmachine4.$group_31'.
     1/1: \cmd__payload__is_read
Creating decoders for process `\bankmachine4.$group_30'.
     1/1: \req__rdata_valid
Creating decoders for process `\bankmachine4.$group_29'.
     1/1: \cmd__payload__we
Creating decoders for process `\bankmachine4.$group_28'.
     1/1: \cmd__payload__is_write
Creating decoders for process `\bankmachine4.$group_27'.
     1/1: \req__wdata_ready
Creating decoders for process `\bankmachine4.$group_26'.
     1/1: \cmd__payload__cas
Creating decoders for process `\bankmachine4.$group_25'.
     1/1: \cmd__valid
Creating decoders for process `\bankmachine4.$group_24'.
     1/1: \fsm_state$next
Creating decoders for process `\bankmachine4.$group_23'.
     1/1: \auto_precharge
Creating decoders for process `\bankmachine4.$group_37'.
     1/1: \refresh_gnt
Creating decoders for process `\bankmachine4.$group_36'.
     1/1: \row_open
Creating decoders for process `\bankmachine4.$group_35'.
     1/1: \row_col_n_addr_sel
Creating decoders for process `\bankmachine4.$group_34'.
     1/1: \cmd__payload__is_cmd
Creating decoders for process `\bankmachine4.$group_18'.
     1/1: \cmd__payload__a
Creating decoders for process `\U$$1$38.$group_3'.
     1/2: \source__payload__addr$next
     2/2: \source__payload__we$next
Creating decoders for process `\U$$1$38.$group_2'.
     1/1: \source__last$next
Creating decoders for process `\U$$1$38.$group_1'.
     1/1: \source__first$next
Creating decoders for process `\U$$1$38.$group_0'.
     1/1: \source__valid$next
Creating decoders for process `\fifo$37.$group_10'.
     1/1: \consume$next
Creating decoders for process `\fifo$37.$group_7'.
     1/1: \produce$next
Creating decoders for process `\fifo$37.$group_11'.
     1/1: \level$next
Creating decoders for process `\trascon$35.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trascon$35.$group_0'.
     1/1: \count$next
Creating decoders for process `\trccon$34.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trccon$34.$group_0'.
     1/1: \count$next
Creating decoders for process `\twtpcon$33.$group_1'.
     1/1: \ready$next
Creating decoders for process `\twtpcon$33.$group_0'.
     1/1: \count$next
Creating decoders for process `\bankmachine3.$group_33'.
     1/1: \cmd__payload__ras
Creating decoders for process `\bankmachine3.$group_16'.
     1/1: \row$next
Creating decoders for process `\bankmachine3.$group_15'.
     1/1: \row_opened$next
Creating decoders for process `\bankmachine3.$group_32'.
     1/1: \row_close
Creating decoders for process `\bankmachine3.$group_31'.
     1/1: \cmd__payload__is_read
Creating decoders for process `\bankmachine3.$group_30'.
     1/1: \req__rdata_valid
Creating decoders for process `\bankmachine3.$group_29'.
     1/1: \cmd__payload__we
Creating decoders for process `\bankmachine3.$group_28'.
     1/1: \cmd__payload__is_write
Creating decoders for process `\bankmachine3.$group_27'.
     1/1: \req__wdata_ready
Creating decoders for process `\bankmachine3.$group_26'.
     1/1: \cmd__payload__cas
Creating decoders for process `\bankmachine3.$group_25'.
     1/1: \cmd__valid
Creating decoders for process `\bankmachine3.$group_24'.
     1/1: \fsm_state$next
Creating decoders for process `\bankmachine3.$group_23'.
     1/1: \auto_precharge
Creating decoders for process `\bankmachine3.$group_37'.
     1/1: \refresh_gnt
Creating decoders for process `\bankmachine3.$group_36'.
     1/1: \row_open
Creating decoders for process `\bankmachine3.$group_35'.
     1/1: \row_col_n_addr_sel
Creating decoders for process `\bankmachine3.$group_34'.
     1/1: \cmd__payload__is_cmd
Creating decoders for process `\bankmachine3.$group_18'.
     1/1: \cmd__payload__a
Creating decoders for process `\U$$1$30.$group_3'.
     1/2: \source__payload__addr$next
     2/2: \source__payload__we$next
Creating decoders for process `\U$$1$30.$group_2'.
     1/1: \source__last$next
Creating decoders for process `\U$$1$30.$group_1'.
     1/1: \source__first$next
Creating decoders for process `\U$$1$30.$group_0'.
     1/1: \source__valid$next
Creating decoders for process `\fifo$29.$group_10'.
     1/1: \consume$next
Creating decoders for process `\fifo$29.$group_7'.
     1/1: \produce$next
Creating decoders for process `\fifo$29.$group_11'.
     1/1: \level$next
Creating decoders for process `\trascon$27.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trascon$27.$group_0'.
     1/1: \count$next
Creating decoders for process `\trccon$26.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trccon$26.$group_0'.
     1/1: \count$next
Creating decoders for process `\twtpcon$25.$group_1'.
     1/1: \ready$next
Creating decoders for process `\twtpcon$25.$group_0'.
     1/1: \count$next
Creating decoders for process `\bankmachine2.$group_33'.
     1/1: \cmd__payload__ras
Creating decoders for process `\bankmachine2.$group_16'.
     1/1: \row$next
Creating decoders for process `\bankmachine2.$group_15'.
     1/1: \row_opened$next
Creating decoders for process `\bankmachine2.$group_32'.
     1/1: \row_close
Creating decoders for process `\bankmachine2.$group_31'.
     1/1: \cmd__payload__is_read
Creating decoders for process `\bankmachine2.$group_30'.
     1/1: \req__rdata_valid
Creating decoders for process `\bankmachine2.$group_29'.
     1/1: \cmd__payload__we
Creating decoders for process `\bankmachine2.$group_28'.
     1/1: \cmd__payload__is_write
Creating decoders for process `\bankmachine2.$group_27'.
     1/1: \req__wdata_ready
Creating decoders for process `\bankmachine2.$group_26'.
     1/1: \cmd__payload__cas
Creating decoders for process `\bankmachine2.$group_25'.
     1/1: \cmd__valid
Creating decoders for process `\bankmachine2.$group_24'.
     1/1: \fsm_state$next
Creating decoders for process `\bankmachine2.$group_23'.
     1/1: \auto_precharge
Creating decoders for process `\bankmachine2.$group_37'.
     1/1: \refresh_gnt
Creating decoders for process `\bankmachine2.$group_36'.
     1/1: \row_open
Creating decoders for process `\bankmachine2.$group_35'.
     1/1: \row_col_n_addr_sel
Creating decoders for process `\bankmachine2.$group_34'.
     1/1: \cmd__payload__is_cmd
Creating decoders for process `\bankmachine2.$group_18'.
     1/1: \cmd__payload__a
Creating decoders for process `\U$$1$22.$group_3'.
     1/2: \source__payload__addr$next
     2/2: \source__payload__we$next
Creating decoders for process `\U$$1$22.$group_2'.
     1/1: \source__last$next
Creating decoders for process `\U$$1$22.$group_1'.
     1/1: \source__first$next
Creating decoders for process `\U$$1$22.$group_0'.
     1/1: \source__valid$next
Creating decoders for process `\fifo$21.$group_10'.
     1/1: \consume$next
Creating decoders for process `\fifo$21.$group_7'.
     1/1: \produce$next
Creating decoders for process `\fifo$21.$group_11'.
     1/1: \level$next
Creating decoders for process `\trascon$19.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trascon$19.$group_0'.
     1/1: \count$next
Creating decoders for process `\trccon$18.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trccon$18.$group_0'.
     1/1: \count$next
Creating decoders for process `\twtpcon$17.$group_1'.
     1/1: \ready$next
Creating decoders for process `\twtpcon$17.$group_0'.
     1/1: \count$next
Creating decoders for process `\bankmachine1.$group_33'.
     1/1: \cmd__payload__ras
Creating decoders for process `\bankmachine1.$group_16'.
     1/1: \row$next
Creating decoders for process `\bankmachine1.$group_15'.
     1/1: \row_opened$next
Creating decoders for process `\bankmachine1.$group_32'.
     1/1: \row_close
Creating decoders for process `\bankmachine1.$group_31'.
     1/1: \cmd__payload__is_read
Creating decoders for process `\bankmachine1.$group_30'.
     1/1: \req__rdata_valid
Creating decoders for process `\bankmachine1.$group_29'.
     1/1: \cmd__payload__we
Creating decoders for process `\bankmachine1.$group_28'.
     1/1: \cmd__payload__is_write
Creating decoders for process `\bankmachine1.$group_27'.
     1/1: \req__wdata_ready
Creating decoders for process `\bankmachine1.$group_26'.
     1/1: \cmd__payload__cas
Creating decoders for process `\bankmachine1.$group_25'.
     1/1: \cmd__valid
Creating decoders for process `\bankmachine1.$group_24'.
     1/1: \fsm_state$next
Creating decoders for process `\bankmachine1.$group_23'.
     1/1: \auto_precharge
Creating decoders for process `\bankmachine1.$group_37'.
     1/1: \refresh_gnt
Creating decoders for process `\bankmachine1.$group_36'.
     1/1: \row_open
Creating decoders for process `\bankmachine1.$group_35'.
     1/1: \row_col_n_addr_sel
Creating decoders for process `\bankmachine1.$group_34'.
     1/1: \cmd__payload__is_cmd
Creating decoders for process `\bankmachine1.$group_18'.
     1/1: \cmd__payload__a
Creating decoders for process `\U$$1$14.$group_3'.
     1/2: \source__payload__addr$next
     2/2: \source__payload__we$next
Creating decoders for process `\U$$1$14.$group_2'.
     1/1: \source__last$next
Creating decoders for process `\U$$1$14.$group_1'.
     1/1: \source__first$next
Creating decoders for process `\U$$1$14.$group_0'.
     1/1: \source__valid$next
Creating decoders for process `\fifo$13.$group_10'.
     1/1: \consume$next
Creating decoders for process `\fifo$13.$group_7'.
     1/1: \produce$next
Creating decoders for process `\fifo$13.$group_11'.
     1/1: \level$next
Creating decoders for process `\trascon$11.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trascon$11.$group_0'.
     1/1: \count$next
Creating decoders for process `\trccon$10.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trccon$10.$group_0'.
     1/1: \count$next
Creating decoders for process `\twtpcon$9.$group_1'.
     1/1: \ready$next
Creating decoders for process `\twtpcon$9.$group_0'.
     1/1: \count$next
Creating decoders for process `\bankmachine0.$group_33'.
     1/1: \cmd__payload__ras
Creating decoders for process `\bankmachine0.$group_16'.
     1/1: \row$next
Creating decoders for process `\bankmachine0.$group_15'.
     1/1: \row_opened$next
Creating decoders for process `\bankmachine0.$group_32'.
     1/1: \row_close
Creating decoders for process `\bankmachine0.$group_31'.
     1/1: \cmd__payload__is_read
Creating decoders for process `\bankmachine0.$group_30'.
     1/1: \req__rdata_valid
Creating decoders for process `\bankmachine0.$group_29'.
     1/1: \cmd__payload__we
Creating decoders for process `\bankmachine0.$group_28'.
     1/1: \cmd__payload__is_write
Creating decoders for process `\bankmachine0.$group_27'.
     1/1: \req__wdata_ready
Creating decoders for process `\bankmachine0.$group_26'.
     1/1: \cmd__payload__cas
Creating decoders for process `\bankmachine0.$group_25'.
     1/1: \cmd__valid
Creating decoders for process `\bankmachine0.$group_24'.
     1/1: \fsm_state$next
Creating decoders for process `\bankmachine0.$group_23'.
     1/1: \auto_precharge
Creating decoders for process `\bankmachine0.$group_37'.
     1/1: \refresh_gnt
Creating decoders for process `\bankmachine0.$group_36'.
     1/1: \row_open
Creating decoders for process `\bankmachine0.$group_35'.
     1/1: \row_col_n_addr_sel
Creating decoders for process `\bankmachine0.$group_34'.
     1/1: \cmd__payload__is_cmd
Creating decoders for process `\bankmachine0.$group_18'.
     1/1: \cmd__payload__a
Creating decoders for process `\U$$1$6.$group_3'.
     1/2: \source__payload__addr$next
     2/2: \source__payload__we$next
Creating decoders for process `\U$$1$6.$group_2'.
     1/1: \source__last$next
Creating decoders for process `\U$$1$6.$group_1'.
     1/1: \source__first$next
Creating decoders for process `\U$$1$6.$group_0'.
     1/1: \source__valid$next
Creating decoders for process `\fifo.$group_10'.
     1/1: \consume$next
Creating decoders for process `\fifo.$group_7'.
     1/1: \produce$next
Creating decoders for process `\fifo.$group_11'.
     1/1: \level$next
Creating decoders for process `\trascon.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trascon.$group_0'.
     1/1: \count$next
Creating decoders for process `\trccon.$group_1'.
     1/1: \ready$next
Creating decoders for process `\trccon.$group_0'.
     1/1: \count$next
Creating decoders for process `\twtpcon.$group_1'.
     1/1: \ready$next
Creating decoders for process `\twtpcon.$group_0'.
     1/1: \count$next
Creating decoders for process `\refresher.$group_4'.
     1/1: \fsm_state$next
Creating decoders for process `\refresher.$group_8'.
     1/1: \cmd__last
Creating decoders for process `\refresher.$group_7'.
     1/1: \zqcs_executer_start
Creating decoders for process `\refresher.$group_6'.
     1/1: \sequencer_start
Creating decoders for process `\refresher.$group_5'.
     1/1: \cmd__valid
Creating decoders for process `\timeline$5.$group_6'.
     1/1: \done$next
Creating decoders for process `\timeline$5.$group_5'.
     1/1: \we$next
Creating decoders for process `\timeline$5.$group_4'.
     1/1: \ras$next
Creating decoders for process `\timeline$5.$group_3'.
     1/1: \cas$next
Creating decoders for process `\timeline$5.$group_2'.
     1/1: \ba$next
Creating decoders for process `\timeline$5.$group_1'.
     1/1: \a$next
Creating decoders for process `\timeline$5.$group_0'.
     1/1: \counter$next
Creating decoders for process `\zqcs_timer.$group_1'.
     1/1: \done$next
Creating decoders for process `\zqcs_timer.$group_0'.
     1/1: \count$next
Creating decoders for process `\sequencer.$group_5'.
     1/1: \count$next
Creating decoders for process `\sequencer.$group_7'.
     1/1: \countDiffZero$next
Creating decoders for process `\sequencer.$group_6'.
     1/1: \countEqZero$next
Creating decoders for process `\timeline.$group_6'.
     1/1: \done$next
Creating decoders for process `\timeline.$group_5'.
     1/1: \we$next
Creating decoders for process `\timeline.$group_4'.
     1/1: \ras$next
Creating decoders for process `\timeline.$group_3'.
     1/1: \cas$next
Creating decoders for process `\timeline.$group_2'.
     1/1: \ba$next
Creating decoders for process `\timeline.$group_1'.
     1/1: \a$next
Creating decoders for process `\timeline.$group_0'.
     1/1: \counter$next
Creating decoders for process `\postponer.$group_1'.
     1/1: \req_o$next
Creating decoders for process `\postponer.$group_0'.
     1/1: \count$next
Creating decoders for process `\timer.$group_1'.
     1/1: \done$next
Creating decoders for process `\timer.$group_0'.
     1/1: \count$next
Creating decoders for process `\dfii.$group_35'.
     1/1: \phase_1_inti__rddata_valid
Creating decoders for process `\dfii.$group_34'.
     1/1: \phase_1_inti__rddata
Creating decoders for process `\dfii.$group_33'.
     1/1: \phase_0_inti__rddata_valid
Creating decoders for process `\dfii.$group_32'.
     1/1: \phase_0_inti__rddata
Creating decoders for process `\dfii.$group_31'.
     1/1: \slave__rddata_valid$32
Creating decoders for process `\dfii.$group_30'.
     1/1: \slave__rddata$31
Creating decoders for process `\dfii.$group_29'.
     1/1: \master__rddata_en$14
Creating decoders for process `\dfii.$group_28'.
     1/1: \master__wrdata_mask$13
Creating decoders for process `\dfii.$group_27'.
     1/1: \master__wrdata_en$12
Creating decoders for process `\dfii.$group_26'.
     1/1: \master__wrdata$11
Creating decoders for process `\dfii.$group_25'.
     1/1: \master__act$10
Creating decoders for process `\dfii.$group_24'.
     1/1: \master__reset$9
Creating decoders for process `\dfii.$group_23'.
     1/1: \master__odt$8
Creating decoders for process `\dfii.$group_22'.
     1/1: \master__clk_en$7
Creating decoders for process `\dfii.$group_21'.
     1/1: \master__we$6
Creating decoders for process `\dfii.$group_20'.
     1/1: \master__ras$5
Creating decoders for process `\dfii.$group_19'.
     1/1: \master__cs_n$4
Creating decoders for process `\dfii.$group_18'.
     1/1: \master__cas$3
Creating decoders for process `\dfii.$group_17'.
     1/1: \master__bank$2
Creating decoders for process `\dfii.$group_16'.
     1/1: \master__address$1
Creating decoders for process `\dfii.$group_15'.
     1/1: \slave__rddata_valid
Creating decoders for process `\dfii.$group_14'.
     1/1: \slave__rddata
Creating decoders for process `\dfii.$group_13'.
     1/1: \master__rddata_en
Creating decoders for process `\dfii.$group_12'.
     1/1: \master__wrdata_mask
Creating decoders for process `\dfii.$group_11'.
     1/1: \master__wrdata_en
Creating decoders for process `\dfii.$group_10'.
     1/1: \master__wrdata
Creating decoders for process `\dfii.$group_9'.
     1/1: \master__act
Creating decoders for process `\dfii.$group_8'.
     1/1: \master__reset
Creating decoders for process `\dfii.$group_7'.
     1/1: \master__odt
Creating decoders for process `\dfii.$group_6'.
     1/1: \master__clk_en
Creating decoders for process `\dfii.$group_5'.
     1/1: \master__we
Creating decoders for process `\dfii.$group_4'.
     1/1: \master__ras
Creating decoders for process `\dfii.$group_3'.
     1/1: \master__cs_n
Creating decoders for process `\dfii.$group_2'.
     1/1: \master__cas
Creating decoders for process `\dfii.$group_1'.
     1/1: \master__bank
Creating decoders for process `\dfii.$group_0'.
     1/1: \master__address
Creating decoders for process `\phase_1.$group_9'.
     1/1: \inti__ras
Creating decoders for process `\phase_1.$group_8'.
     1/1: \inti__cas
Creating decoders for process `\phase_1.$group_7'.
     1/1: \inti__we
Creating decoders for process `\phase_1.$group_6'.
     1/1: \inti__cs_n
Creating decoders for process `\phase_1.$group_10'.
     1/1: \dfii_p1_rddata__r_data$next
Creating decoders for process `\phase_0.$group_9'.
     1/1: \inti__ras
Creating decoders for process `\phase_0.$group_8'.
     1/1: \inti__cas
Creating decoders for process `\phase_0.$group_7'.
     1/1: \inti__we
Creating decoders for process `\phase_0.$group_6'.
     1/1: \inti__cs_n
Creating decoders for process `\phase_0.$group_10'.
     1/1: \dfii_p0_rddata__r_data$next
Creating decoders for process `\wb_decoder$4.$group_5'.
     1/1: \wb__cyc
Creating decoders for process `\wb_decoder$4.$group_6'.
     1/1: \_bus__dat_r
Creating decoders for process `\csr_bridge_0$3.$group_5'.
     1/1: \cycle$next
Creating decoders for process `\csr_bridge_0$3.$group_4'.
     1/1: \csr__w_stb
Creating decoders for process `\csr_bridge_0$3.$group_3'.
     1/1: \csr__w_data
Creating decoders for process `\csr_bridge_0$3.$group_2'.
     1/1: \csr__r_stb
Creating decoders for process `\csr_bridge_0$3.$group_7'.
     1/1: \wb__ack$next
Creating decoders for process `\csr_bridge_0$3.$group_6'.
     1/4: \wb__dat_r$next [31:24]
     2/4: \wb__dat_r$next [15:8]
     3/4: \wb__dat_r$next [7:0]
     4/4: \wb__dat_r$next [23:16]
Creating decoders for process `\csr_mux_0$2.$group_36'.
     1/1: \dfii_p1_rddata__shadow_en$next
Creating decoders for process `\csr_mux_0$2.$group_26'.
     1/1: \dfii_p1_command_issue__shadow$next
Creating decoders for process `\csr_mux_0$2.$group_25'.
     1/1: \dfii_p1_command_issue__w_stb$next
Creating decoders for process `\csr_mux_0$2.$group_35'.
     1/8: \dfii_p1_wrdata__shadow$next [63:56]
     2/8: \dfii_p1_wrdata__shadow$next [47:40]
     3/8: \dfii_p1_wrdata__shadow$next [39:32]
     4/8: \dfii_p1_wrdata__shadow$next [31:24]
     5/8: \dfii_p1_wrdata__shadow$next [23:16]
     6/8: \dfii_p1_wrdata__shadow$next [15:8]
     7/8: \dfii_p1_wrdata__shadow$next [7:0]
     8/8: \dfii_p1_wrdata__shadow$next [55:48]
Creating decoders for process `\csr_mux_0$2.$group_23'.
     1/1: \dfii_p1_command__shadow$next
Creating decoders for process `\csr_mux_0$2.$group_22'.
     1/1: \dfii_p1_command__w_stb$next
Creating decoders for process `\csr_mux_0$2.$group_34'.
     1/1: \dfii_p1_wrdata__w_stb$next
Creating decoders for process `\csr_mux_0$2.$group_20'.
     1/1: \dfii_p0_rddata__shadow$next
Creating decoders for process `\csr_mux_0$2.$group_19'.
     1/1: \dfii_p0_rddata__r_stb
Creating decoders for process `\csr_mux_0$2.$group_18'.
     1/1: \dfii_p0_rddata__shadow_en$next
Creating decoders for process `\csr_mux_0$2.$group_17'.
     1/8: \dfii_p0_wrdata__shadow$next [63:56]
     2/8: \dfii_p0_wrdata__shadow$next [47:40]
     3/8: \dfii_p0_wrdata__shadow$next [39:32]
     4/8: \dfii_p0_wrdata__shadow$next [31:24]
     5/8: \dfii_p0_wrdata__shadow$next [23:16]
     6/8: \dfii_p0_wrdata__shadow$next [15:8]
     7/8: \dfii_p0_wrdata__shadow$next [7:0]
     8/8: \dfii_p0_wrdata__shadow$next [55:48]
Creating decoders for process `\csr_mux_0$2.$group_16'.
     1/1: \dfii_p0_wrdata__w_stb$next
Creating decoders for process `\csr_mux_0$2.$group_38'.
     1/1: \dfii_p1_rddata__shadow$next
Creating decoders for process `\csr_mux_0$2.$group_14'.
     1/1: \dfii_p0_baddress__shadow$next
Creating decoders for process `\csr_mux_0$2.$group_13'.
     1/1: \dfii_p0_baddress__w_stb$next
Creating decoders for process `\csr_mux_0$2.$group_32'.
     1/1: \dfii_p1_baddress__shadow$next
Creating decoders for process `\csr_mux_0$2.$group_11'.
     1/2: \dfii_p0_address__shadow$next [12:8]
     2/2: \dfii_p0_address__shadow$next [7:0]
Creating decoders for process `\csr_mux_0$2.$group_10'.
     1/1: \dfii_p0_address__w_stb$next
Creating decoders for process `\csr_mux_0$2.$group_31'.
     1/1: \dfii_p1_baddress__w_stb$next
Creating decoders for process `\csr_mux_0$2.$group_8'.
     1/1: \dfii_p0_command_issue__shadow$next
Creating decoders for process `\csr_mux_0$2.$group_7'.
     1/1: \dfii_p0_command_issue__w_stb$next
Creating decoders for process `\csr_mux_0$2.$group_37'.
     1/1: \dfii_p1_rddata__r_stb
Creating decoders for process `\csr_mux_0$2.$group_5'.
     1/1: \dfii_p0_command__shadow$next
Creating decoders for process `\csr_mux_0$2.$group_4'.
     1/1: \dfii_p0_command__w_stb$next
Creating decoders for process `\csr_mux_0$2.$group_29'.
     1/2: \dfii_p1_address__shadow$next [12:8]
     2/2: \dfii_p1_address__shadow$next [7:0]
Creating decoders for process `\csr_mux_0$2.$group_2'.
     1/1: \dfii_control__shadow$next
Creating decoders for process `\csr_mux_0$2.$group_1'.
     1/1: \dfii_control__w_stb$next
Creating decoders for process `\csr_mux_0$2.$group_28'.
     1/1: \dfii_p1_address__w_stb$next
Creating decoders for process `\ddrphy.$group_122'.
Creating decoders for process `\ddrphy.$group_89'.
     1/1: \dq_o_data_muxed$48$next
Creating decoders for process `\ddrphy.$group_88'.
Creating decoders for process `\ddrphy.$group_139'.
     1/1: \wrdata_en_last$next
Creating decoders for process `\ddrphy.$group_86'.
     1/1: \dq_o_data_muxed$38$next
Creating decoders for process `\ddrphy.$group_85'.
Creating decoders for process `\ddrphy.$group_120'.
     1/1: \dq_o_data_muxed$159$next
Creating decoders for process `\ddrphy.$group_83'.
     1/1: \dq_o_data_muxed$28$next
Creating decoders for process `\ddrphy.$group_82'.
Creating decoders for process `\ddrphy.$group_119'.
Creating decoders for process `\ddrphy.$group_80'.
     1/64: \ecp5phy__rddata$12$next [63]
     2/64: \ecp5phy__rddata$12$next [61]
     3/64: \ecp5phy__rddata$12$next [45]
     4/64: \ecp5phy__rddata$12$next [29]
     5/64: \ecp5phy__rddata$12$next [13]
     6/64: \ecp5phy__rddata$12$next [60]
     7/64: \ecp5phy__rddata$12$next [44]
     8/64: \ecp5phy__rddata$12$next [28]
     9/64: \ecp5phy__rddata$12$next [12]
    10/64: \ecp5phy__rddata$12$next [59]
    11/64: \ecp5phy__rddata$12$next [43]
    12/64: \ecp5phy__rddata$12$next [27]
    13/64: \ecp5phy__rddata$12$next [11]
    14/64: \ecp5phy__rddata$12$next [58]
    15/64: \ecp5phy__rddata$12$next [42]
    16/64: \ecp5phy__rddata$12$next [26]
    17/64: \ecp5phy__rddata$12$next [10]
    18/64: \ecp5phy__rddata$12$next [57]
    19/64: \ecp5phy__rddata$12$next [41]
    20/64: \ecp5phy__rddata$12$next [25]
    21/64: \ecp5phy__rddata$12$next [9]
    22/64: \ecp5phy__rddata$12$next [56]
    23/64: \ecp5phy__rddata$12$next [40]
    24/64: \ecp5phy__rddata$12$next [24]
    25/64: \ecp5phy__rddata$12$next [8]
    26/64: \ecp5phy__rddata$12$next [55]
    27/64: \ecp5phy__rddata$12$next [39]
    28/64: \ecp5phy__rddata$12$next [23]
    29/64: \ecp5phy__rddata$12$next [7]
    30/64: \ecp5phy__rddata$12$next [54]
    31/64: \ecp5phy__rddata$12$next [38]
    32/64: \ecp5phy__rddata$12$next [22]
    33/64: \ecp5phy__rddata$12$next [6]
    34/64: \ecp5phy__rddata$12$next [53]
    35/64: \ecp5phy__rddata$12$next [37]
    36/64: \ecp5phy__rddata$12$next [21]
    37/64: \ecp5phy__rddata$12$next [5]
    38/64: \ecp5phy__rddata$12$next [52]
    39/64: \ecp5phy__rddata$12$next [36]
    40/64: \ecp5phy__rddata$12$next [20]
    41/64: \ecp5phy__rddata$12$next [4]
    42/64: \ecp5phy__rddata$12$next [51]
    43/64: \ecp5phy__rddata$12$next [35]
    44/64: \ecp5phy__rddata$12$next [19]
    45/64: \ecp5phy__rddata$12$next [3]
    46/64: \ecp5phy__rddata$12$next [50]
    47/64: \ecp5phy__rddata$12$next [34]
    48/64: \ecp5phy__rddata$12$next [18]
    49/64: \ecp5phy__rddata$12$next [2]
    50/64: \ecp5phy__rddata$12$next [49]
    51/64: \ecp5phy__rddata$12$next [33]
    52/64: \ecp5phy__rddata$12$next [17]
    53/64: \ecp5phy__rddata$12$next [1]
    54/64: \ecp5phy__rddata$12$next [48]
    55/64: \ecp5phy__rddata$12$next [32]
    56/64: \ecp5phy__rddata$12$next [16]
    57/64: \ecp5phy__rddata$12$next [0]
    58/64: \ecp5phy__rddata$12$next [47]
    59/64: \ecp5phy__rddata$12$next [14]
    60/64: \ecp5phy__rddata$12$next [31]
    61/64: \ecp5phy__rddata$12$next [46]
    62/64: \ecp5phy__rddata$12$next [15]
    63/64: \ecp5phy__rddata$12$next [30]
    64/64: \ecp5phy__rddata$12$next [62]
Creating decoders for process `\ddrphy.$group_79'.
     1/64: \ecp5phy__rddata$next [63]
     2/64: \ecp5phy__rddata$next [61]
     3/64: \ecp5phy__rddata$next [45]
     4/64: \ecp5phy__rddata$next [29]
     5/64: \ecp5phy__rddata$next [13]
     6/64: \ecp5phy__rddata$next [60]
     7/64: \ecp5phy__rddata$next [44]
     8/64: \ecp5phy__rddata$next [28]
     9/64: \ecp5phy__rddata$next [12]
    10/64: \ecp5phy__rddata$next [59]
    11/64: \ecp5phy__rddata$next [43]
    12/64: \ecp5phy__rddata$next [27]
    13/64: \ecp5phy__rddata$next [11]
    14/64: \ecp5phy__rddata$next [58]
    15/64: \ecp5phy__rddata$next [42]
    16/64: \ecp5phy__rddata$next [26]
    17/64: \ecp5phy__rddata$next [10]
    18/64: \ecp5phy__rddata$next [57]
    19/64: \ecp5phy__rddata$next [41]
    20/64: \ecp5phy__rddata$next [25]
    21/64: \ecp5phy__rddata$next [9]
    22/64: \ecp5phy__rddata$next [56]
    23/64: \ecp5phy__rddata$next [40]
    24/64: \ecp5phy__rddata$next [24]
    25/64: \ecp5phy__rddata$next [8]
    26/64: \ecp5phy__rddata$next [55]
    27/64: \ecp5phy__rddata$next [39]
    28/64: \ecp5phy__rddata$next [23]
    29/64: \ecp5phy__rddata$next [7]
    30/64: \ecp5phy__rddata$next [54]
    31/64: \ecp5phy__rddata$next [38]
    32/64: \ecp5phy__rddata$next [22]
    33/64: \ecp5phy__rddata$next [6]
    34/64: \ecp5phy__rddata$next [53]
    35/64: \ecp5phy__rddata$next [37]
    36/64: \ecp5phy__rddata$next [21]
    37/64: \ecp5phy__rddata$next [5]
    38/64: \ecp5phy__rddata$next [52]
    39/64: \ecp5phy__rddata$next [36]
    40/64: \ecp5phy__rddata$next [20]
    41/64: \ecp5phy__rddata$next [4]
    42/64: \ecp5phy__rddata$next [51]
    43/64: \ecp5phy__rddata$next [35]
    44/64: \ecp5phy__rddata$next [19]
    45/64: \ecp5phy__rddata$next [3]
    46/64: \ecp5phy__rddata$next [50]
    47/64: \ecp5phy__rddata$next [34]
    48/64: \ecp5phy__rddata$next [18]
    49/64: \ecp5phy__rddata$next [2]
    50/64: \ecp5phy__rddata$next [49]
    51/64: \ecp5phy__rddata$next [33]
    52/64: \ecp5phy__rddata$next [17]
    53/64: \ecp5phy__rddata$next [1]
    54/64: \ecp5phy__rddata$next [48]
    55/64: \ecp5phy__rddata$next [32]
    56/64: \ecp5phy__rddata$next [16]
    57/64: \ecp5phy__rddata$next [0]
    58/64: \ecp5phy__rddata$next [47]
    59/64: \ecp5phy__rddata$next [14]
    60/64: \ecp5phy__rddata$next [31]
    61/64: \ecp5phy__rddata$next [46]
    62/64: \ecp5phy__rddata$next [15]
    63/64: \ecp5phy__rddata$next [30]
    64/64: \ecp5phy__rddata$next [62]
Creating decoders for process `\ddrphy.$group_78'.
     1/1: \dq_o_data_muxed$next
Creating decoders for process `\ddrphy.$group_77'.
Creating decoders for process `\ddrphy.$group_131'.
     1/1: \rddata_en_last$next
Creating decoders for process `\ddrphy.$group_75'.
     1/1: \dm_o_data_muxed$next
Creating decoders for process `\ddrphy.$group_74'.
Creating decoders for process `\ddrphy.$group_117'.
     1/1: \dq_o_data_muxed$149$next
Creating decoders for process `\ddrphy.$group_72'.
     1/1: \datavalid_prev$next
Creating decoders for process `\ddrphy.$group_116'.
Creating decoders for process `\ddrphy.$group_145'.
Creating decoders for process `\ddrphy.$group_114'.
     1/1: \dq_o_data_muxed$139$next
Creating decoders for process `\ddrphy.$group_113'.
Creating decoders for process `\ddrphy.$group_129'.
     1/1: \dq_o_data_muxed$189$next
Creating decoders for process `\ddrphy.$group_111'.
     1/1: \dq_o_data_muxed$129$next
Creating decoders for process `\ddrphy.$group_110'.
Creating decoders for process `\ddrphy.$group_128'.
Creating decoders for process `\ddrphy.$group_108'.
     1/1: \dq_o_data_muxed$119$next
Creating decoders for process `\ddrphy.$group_107'.
Creating decoders for process `\ddrphy.$group_146'.
Creating decoders for process `\ddrphy.$group_105'.
     1/1: \dm_o_data_muxed$108$next
Creating decoders for process `\ddrphy.$group_104'.
Creating decoders for process `\ddrphy.$group_126'.
     1/1: \dq_o_data_muxed$179$next
Creating decoders for process `\ddrphy.$group_102'.
     1/1: \datavalid_prev$250$next
Creating decoders for process `\ddrphy.$group_101'.
     1/1: \dq_o_data_muxed$88$next
Creating decoders for process `\ddrphy.$group_100'.
Creating decoders for process `\ddrphy.$group_125'.
Creating decoders for process `\ddrphy.$group_98'.
     1/1: \dq_o_data_muxed$78$next
Creating decoders for process `\ddrphy.$group_97'.
Creating decoders for process `\ddrphy.$group_133'.
     1/1: \rddata_valid$next
Creating decoders for process `\ddrphy.$group_95'.
     1/1: \dq_o_data_muxed$68$next
Creating decoders for process `\ddrphy.$group_94'.
Creating decoders for process `\ddrphy.$group_123'.
     1/1: \dq_o_data_muxed$169$next
Creating decoders for process `\ddrphy.$group_92'.
     1/1: \dq_o_data_muxed$58$next
Creating decoders for process `\ddrphy.$group_1'.
     1/2: \burstdet_reg$next [1]
     2/2: \burstdet_reg$next [0]
Creating decoders for process `\ddrphy.$group_91'.
Creating decoders for process `\dqsbufm_manager1.$group_2'.
     1/1: \readclksel$next
Creating decoders for process `\dqsbufm_manager1.$group_1'.
     1/1: \fsm_state$next
Creating decoders for process `\dqsbufm_manager1.$group_0'.
     1/1: \pause$next
Creating decoders for process `\dqsbufm_manager0.$group_2'.
     1/1: \readclksel$next
Creating decoders for process `\dqsbufm_manager0.$group_1'.
     1/1: \fsm_state$next
Creating decoders for process `\dqsbufm_manager0.$group_0'.
     1/1: \pause$next
Creating decoders for process `\init.$group_0'.
     1/1: \lock_d$next
Creating decoders for process `\U$$2.$group_5'.
     1/1: \update$next
Creating decoders for process `\U$$2.$group_4'.
     1/1: \pause$next
Creating decoders for process `\U$$2.$group_3'.
     1/1: \reset$next
Creating decoders for process `\U$$2.$group_2'.
     1/1: \stop$next
Creating decoders for process `\U$$2.$group_1'.
     1/1: \freeze$next
Creating decoders for process `\U$$2.$group_0'.
     1/1: \counter$next
Creating decoders for process `\U$$1.$group_1'.
Creating decoders for process `\U$$1.$group_0'.
Creating decoders for process `\wb_decoder.$group_5'.
     1/1: \wb__cyc
Creating decoders for process `\wb_decoder.$group_6'.
     1/1: \_bus__dat_r
Creating decoders for process `\csr_bridge_0.$group_5'.
     1/1: \cycle$next
Creating decoders for process `\csr_bridge_0.$group_4'.
     1/1: \csr__w_stb
Creating decoders for process `\csr_bridge_0.$group_3'.
     1/1: \csr__w_data
Creating decoders for process `\csr_bridge_0.$group_2'.
     1/1: \csr__r_stb
Creating decoders for process `\csr_bridge_0.$group_7'.
     1/1: \wb__ack$next
Creating decoders for process `\csr_bridge_0.$group_6'.
     1/4: \wb__dat_r$next [31:24]
     2/4: \wb__dat_r$next [15:8]
     3/4: \wb__dat_r$next [7:0]
     4/4: \wb__dat_r$next [23:16]
Creating decoders for process `\csr_mux_0.$group_15'.
     1/1: \bitslip__shadow_en$next
Creating decoders for process `\csr_mux_0.$group_14'.
     1/1: \rdly_p1__shadow$next
Creating decoders for process `\csr_mux_0.$group_13'.
     1/1: \rdly_p1__r_stb
Creating decoders for process `\csr_mux_0.$group_12'.
     1/1: \rdly_p1__w_stb$next
Creating decoders for process `\csr_mux_0.$group_18'.
     1/1: \bitslip__r_stb
Creating decoders for process `\csr_mux_0.$group_10'.
     1/1: \rdly_p1__shadow_en$next
Creating decoders for process `\csr_mux_0.$group_9'.
     1/1: \rdly_p0__shadow$next
Creating decoders for process `\csr_mux_0.$group_8'.
     1/1: \rdly_p0__r_stb
Creating decoders for process `\csr_mux_0.$group_7'.
     1/1: \rdly_p0__w_stb$next
Creating decoders for process `\csr_mux_0.$group_17'.
     1/1: \bitslip__w_stb$next
Creating decoders for process `\csr_mux_0.$group_5'.
     1/1: \rdly_p0__shadow_en$next
Creating decoders for process `\csr_mux_0.$group_4'.
     1/1: \burstdet__shadow$next
Creating decoders for process `\csr_mux_0.$group_3'.
     1/1: \burstdet__r_stb
Creating decoders for process `\csr_mux_0.$group_2'.
     1/1: \burstdet__w_stb$next
Creating decoders for process `\csr_mux_0.$group_19'.
     1/1: \bitslip__shadow$next
Creating decoders for process `\csr_mux_0.$group_0'.
     1/1: \burstdet__shadow_en$next
Creating decoders for process `\decoder.$group_15'.
     1/1: \_bus__cyc$11
Creating decoders for process `\decoder.$group_18'.
     1/1: \bus__cyc
Creating decoders for process `\decoder.$group_17'.
     1/1: \_bus__cyc$13
Creating decoders for process `\decoder.$group_16'.
     1/1: \_bus__dat_r
Creating decoders for process `\sysclk.$group_1'.
     1/1: \podcnt$next
Creating decoders for process `\sysclk.$group_2'.

10. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\drambone.$group_8'.
Removing empty process `drambone.$group_8'.
Found and cleaned up 1 empty switch in `\drambone.$group_7'.
Removing empty process `drambone.$group_7'.
Found and cleaned up 1 empty switch in `\drambone.$group_6'.
Removing empty process `drambone.$group_6'.
Found and cleaned up 1 empty switch in `\drambone.$group_5'.
Removing empty process `drambone.$group_5'.
Found and cleaned up 3 empty switches in `\drambone.$group_10'.
Removing empty process `drambone.$group_10'.
Found and cleaned up 1 empty switch in `\drambone.$group_3'.
Removing empty process `drambone.$group_3'.
Found and cleaned up 1 empty switch in `\drambone.$group_2'.
Removing empty process `drambone.$group_2'.
Found and cleaned up 1 empty switch in `\drambone.$group_1'.
Removing empty process `drambone.$group_1'.
Found and cleaned up 6 empty switches in `\drambone.$group_9'.
Removing empty process `drambone.$group_9'.
Found and cleaned up 1 empty switch in `\crossbar.$group_39'.
Removing empty process `crossbar.$group_39'.
Found and cleaned up 1 empty switch in `\crossbar.$group_24'.
Removing empty process `crossbar.$group_24'.
Found and cleaned up 1 empty switch in `\crossbar.$group_23'.
Removing empty process `crossbar.$group_23'.
Found and cleaned up 1 empty switch in `\crossbar.$group_22'.
Removing empty process `crossbar.$group_22'.
Found and cleaned up 1 empty switch in `\crossbar.$group_32'.
Removing empty process `crossbar.$group_32'.
Found and cleaned up 1 empty switch in `\crossbar.$group_20'.
Removing empty process `crossbar.$group_20'.
Found and cleaned up 1 empty switch in `\crossbar.$group_19'.
Removing empty process `crossbar.$group_19'.
Found and cleaned up 1 empty switch in `\crossbar.$group_18'.
Removing empty process `crossbar.$group_18'.
Found and cleaned up 1 empty switch in `\crossbar.$group_31'.
Removing empty process `crossbar.$group_31'.
Found and cleaned up 1 empty switch in `\crossbar.$group_16'.
Removing empty process `crossbar.$group_16'.
Found and cleaned up 1 empty switch in `\crossbar.$group_15'.
Removing empty process `crossbar.$group_15'.
Found and cleaned up 1 empty switch in `\crossbar.$group_14'.
Removing empty process `crossbar.$group_14'.
Found and cleaned up 1 empty switch in `\crossbar.$group_30'.
Removing empty process `crossbar.$group_30'.
Found and cleaned up 1 empty switch in `\crossbar.$group_12'.
Removing empty process `crossbar.$group_12'.
Found and cleaned up 1 empty switch in `\crossbar.$group_11'.
Removing empty process `crossbar.$group_11'.
Found and cleaned up 1 empty switch in `\crossbar.$group_10'.
Removing empty process `crossbar.$group_10'.
Found and cleaned up 1 empty switch in `\crossbar.$group_38'.
Removing empty process `crossbar.$group_38'.
Found and cleaned up 1 empty switch in `\crossbar.$group_8'.
Removing empty process `crossbar.$group_8'.
Found and cleaned up 1 empty switch in `\crossbar.$group_7'.
Removing empty process `crossbar.$group_7'.
Found and cleaned up 1 empty switch in `\crossbar.$group_6'.
Removing empty process `crossbar.$group_6'.
Found and cleaned up 1 empty switch in `\crossbar.$group_28'.
Removing empty process `crossbar.$group_28'.
Found and cleaned up 1 empty switch in `\crossbar.$group_4'.
Removing empty process `crossbar.$group_4'.
Found and cleaned up 1 empty switch in `\crossbar.$group_3'.
Removing empty process `crossbar.$group_3'.
Found and cleaned up 1 empty switch in `\crossbar.$group_2'.
Removing empty process `crossbar.$group_2'.
Found and cleaned up 1 empty switch in `\crossbar.$group_27'.
Removing empty process `crossbar.$group_27'.
Found and cleaned up 1 empty switch in `\crossbar.$group_26'.
Removing empty process `crossbar.$group_26'.
Found and cleaned up 1 empty switch in `\U$$9.$group_0'.
Removing empty process `U$$9.$group_0'.
Found and cleaned up 1 empty switch in `\U$$8.$group_0'.
Removing empty process `U$$8.$group_0'.
Found and cleaned up 2 empty switches in `\U$$7.$group_0'.
Removing empty process `U$$7.$group_0'.
Found and cleaned up 2 empty switches in `\U$$6.$group_0'.
Removing empty process `U$$6.$group_0'.
Found and cleaned up 2 empty switches in `\U$$5.$group_0'.
Removing empty process `U$$5.$group_0'.
Found and cleaned up 2 empty switches in `\U$$4.$group_0'.
Removing empty process `U$$4.$group_0'.
Found and cleaned up 2 empty switches in `\U$$3.$group_0'.
Removing empty process `U$$3.$group_0'.
Found and cleaned up 2 empty switches in `\U$$2$66.$group_0'.
Removing empty process `U$$2$66.$group_0'.
Found and cleaned up 2 empty switches in `\U$$1$65.$group_0'.
Removing empty process `U$$1$65.$group_0'.
Found and cleaned up 2 empty switches in `\U$$0$64.$group_0'.
Removing empty process `U$$0$64.$group_0'.
Found and cleaned up 1 empty switch in `\multiplexer.$group_34'.
Removing empty process `multiplexer.$group_34'.
Found and cleaned up 1 empty switch in `\multiplexer.$group_33'.
Removing empty process `multiplexer.$group_33'.
Found and cleaned up 1 empty switch in `\multiplexer.$group_32'.
Removing empty process `multiplexer.$group_32'.
Found and cleaned up 1 empty switch in `\multiplexer.$group_31'.
Removing empty process `multiplexer.$group_31'.
Found and cleaned up 1 empty switch in `\multiplexer.$group_30'.
Removing empty process `multiplexer.$group_30'.
Found and cleaned up 1 empty switch in `\multiplexer.$group_40'.
Removing empty process `multiplexer.$group_40'.
Found and cleaned up 1 empty switch in `\multiplexer.$group_39'.
Removing empty process `multiplexer.$group_39'.
Found and cleaned up 1 empty switch in `\multiplexer.$group_38'.
Removing empty process `multiplexer.$group_38'.
Found and cleaned up 10 empty switches in `\multiplexer.$group_37'.
Removing empty process `multiplexer.$group_37'.
Found and cleaned up 1 empty switch in `\multiplexer.$group_36'.
Removing empty process `multiplexer.$group_36'.
Found and cleaned up 1 empty switch in `\multiplexer.$group_35'.
Removing empty process `multiplexer.$group_35'.
Found and cleaned up 3 empty switches in `\write_antistarvation.$group_1'.
Removing empty process `write_antistarvation.$group_1'.
Found and cleaned up 2 empty switches in `\write_antistarvation.$group_0'.
Removing empty process `write_antistarvation.$group_0'.
Found and cleaned up 3 empty switches in `\read_antistarvation.$group_1'.
Removing empty process `read_antistarvation.$group_1'.
Found and cleaned up 2 empty switches in `\read_antistarvation.$group_0'.
Removing empty process `read_antistarvation.$group_0'.
Found and cleaned up 3 empty switches in `\twtrcon.$group_1'.
Removing empty process `twtrcon.$group_1'.
Found and cleaned up 2 empty switches in `\twtrcon.$group_0'.
Removing empty process `twtrcon.$group_0'.
Found and cleaned up 3 empty switches in `\tccdcon.$group_1'.
Removing empty process `tccdcon.$group_1'.
Found and cleaned up 2 empty switches in `\tccdcon.$group_0'.
Removing empty process `tccdcon.$group_0'.
Found and cleaned up 3 empty switches in `\tfawcon.$group_2'.
Removing empty process `tfawcon.$group_2'.
Found and cleaned up 1 empty switch in `\tfawcon.$group_0'.
Removing empty process `tfawcon.$group_0'.
Found and cleaned up 3 empty switches in `\trrdcon.$group_1'.
Removing empty process `trrdcon.$group_1'.
Found and cleaned up 2 empty switches in `\trrdcon.$group_0'.
Removing empty process `trrdcon.$group_0'.
Found and cleaned up 2 empty switches in `\steerer.$group_15'.
Removing empty process `steerer.$group_15'.
Found and cleaned up 1 empty switch in `\steerer.$group_14'.
Removing empty process `steerer.$group_14'.
Found and cleaned up 2 empty switches in `\steerer.$group_21'.
Removing empty process `steerer.$group_21'.
Found and cleaned up 2 empty switches in `\steerer.$group_20'.
Removing empty process `steerer.$group_20'.
Found and cleaned up 2 empty switches in `\steerer.$group_19'.
Removing empty process `steerer.$group_19'.
Found and cleaned up 2 empty switches in `\steerer.$group_10'.
Removing empty process `steerer.$group_10'.
Found and cleaned up 2 empty switches in `\steerer.$group_9'.
Removing empty process `steerer.$group_9'.
Found and cleaned up 2 empty switches in `\steerer.$group_8'.
Removing empty process `steerer.$group_8'.
Found and cleaned up 2 empty switches in `\steerer.$group_7'.
Removing empty process `steerer.$group_7'.
Found and cleaned up 2 empty switches in `\steerer.$group_6'.
Removing empty process `steerer.$group_6'.
Found and cleaned up 2 empty switches in `\steerer.$group_5'.
Removing empty process `steerer.$group_5'.
Found and cleaned up 2 empty switches in `\steerer.$group_4'.
Removing empty process `steerer.$group_4'.
Found and cleaned up 1 empty switch in `\steerer.$group_3'.
Removing empty process `steerer.$group_3'.
Found and cleaned up 2 empty switches in `\steerer.$group_18'.
Removing empty process `steerer.$group_18'.
Found and cleaned up 2 empty switches in `\steerer.$group_17'.
Removing empty process `steerer.$group_17'.
Found and cleaned up 2 empty switches in `\steerer.$group_16'.
Removing empty process `steerer.$group_16'.
Found and cleaned up 2 empty switches in `\choose_req.$group_9'.
Removing empty process `choose_req.$group_9'.
Found and cleaned up 2 empty switches in `\choose_req.$group_8'.
Removing empty process `choose_req.$group_8'.
Found and cleaned up 1 empty switch in `\choose_req.$group_7'.
Removing empty process `choose_req.$group_7'.
Found and cleaned up 1 empty switch in `\choose_req.$group_6'.
Removing empty process `choose_req.$group_6'.
Found and cleaned up 1 empty switch in `\choose_req.$group_5'.
Removing empty process `choose_req.$group_5'.
Found and cleaned up 1 empty switch in `\choose_req.$group_4'.
Removing empty process `choose_req.$group_4'.
Found and cleaned up 1 empty switch in `\choose_req.$group_3'.
Removing empty process `choose_req.$group_3'.
Found and cleaned up 1 empty switch in `\choose_req.$group_2'.
Removing empty process `choose_req.$group_2'.
Found and cleaned up 8 empty switches in `\choose_req.$group_11'.
Removing empty process `choose_req.$group_11'.
Found and cleaned up 2 empty switches in `\choose_req.$group_10'.
Removing empty process `choose_req.$group_10'.
Found and cleaned up 2 empty switches in `\arbiter$63.$group_1'.
Removing empty process `arbiter$63.$group_1'.
Found and cleaned up 59 empty switches in `\arbiter$63.$group_0'.
Removing empty process `arbiter$63.$group_0'.
Found and cleaned up 2 empty switches in `\choose_cmd.$group_9'.
Removing empty process `choose_cmd.$group_9'.
Found and cleaned up 2 empty switches in `\choose_cmd.$group_8'.
Removing empty process `choose_cmd.$group_8'.
Found and cleaned up 1 empty switch in `\choose_cmd.$group_7'.
Removing empty process `choose_cmd.$group_7'.
Found and cleaned up 1 empty switch in `\choose_cmd.$group_6'.
Removing empty process `choose_cmd.$group_6'.
Found and cleaned up 1 empty switch in `\choose_cmd.$group_5'.
Removing empty process `choose_cmd.$group_5'.
Found and cleaned up 1 empty switch in `\choose_cmd.$group_4'.
Removing empty process `choose_cmd.$group_4'.
Found and cleaned up 1 empty switch in `\choose_cmd.$group_3'.
Removing empty process `choose_cmd.$group_3'.
Found and cleaned up 1 empty switch in `\choose_cmd.$group_2'.
Removing empty process `choose_cmd.$group_2'.
Found and cleaned up 8 empty switches in `\choose_cmd.$group_11'.
Removing empty process `choose_cmd.$group_11'.
Found and cleaned up 2 empty switches in `\choose_cmd.$group_10'.
Removing empty process `choose_cmd.$group_10'.
Found and cleaned up 2 empty switches in `\arbiter.$group_1'.
Removing empty process `arbiter.$group_1'.
Found and cleaned up 59 empty switches in `\arbiter.$group_0'.
Removing empty process `arbiter.$group_0'.
Found and cleaned up 4 empty switches in `\bankmachine7.$group_33'.
Removing empty process `bankmachine7.$group_33'.
Found and cleaned up 2 empty switches in `\bankmachine7.$group_16'.
Removing empty process `bankmachine7.$group_16'.
Found and cleaned up 2 empty switches in `\bankmachine7.$group_15'.
Removing empty process `bankmachine7.$group_15'.
Found and cleaned up 1 empty switch in `\bankmachine7.$group_32'.
Removing empty process `bankmachine7.$group_32'.
Found and cleaned up 5 empty switches in `\bankmachine7.$group_31'.
Removing empty process `bankmachine7.$group_31'.
Found and cleaned up 5 empty switches in `\bankmachine7.$group_30'.
Removing empty process `bankmachine7.$group_30'.
Found and cleaned up 7 empty switches in `\bankmachine7.$group_29'.
Removing empty process `bankmachine7.$group_29'.
Found and cleaned up 5 empty switches in `\bankmachine7.$group_28'.
Removing empty process `bankmachine7.$group_28'.
Found and cleaned up 5 empty switches in `\bankmachine7.$group_27'.
Removing empty process `bankmachine7.$group_27'.
Found and cleaned up 4 empty switches in `\bankmachine7.$group_26'.
Removing empty process `bankmachine7.$group_26'.
Found and cleaned up 7 empty switches in `\bankmachine7.$group_25'.
Removing empty process `bankmachine7.$group_25'.
Found and cleaned up 15 empty switches in `\bankmachine7.$group_24'.
Removing empty process `bankmachine7.$group_24'.
Found and cleaned up 2 empty switches in `\bankmachine7.$group_23'.
Removing empty process `bankmachine7.$group_23'.
Found and cleaned up 2 empty switches in `\bankmachine7.$group_37'.
Removing empty process `bankmachine7.$group_37'.
Found and cleaned up 2 empty switches in `\bankmachine7.$group_36'.
Removing empty process `bankmachine7.$group_36'.
Found and cleaned up 2 empty switches in `\bankmachine7.$group_35'.
Removing empty process `bankmachine7.$group_35'.
Found and cleaned up 4 empty switches in `\bankmachine7.$group_34'.
Removing empty process `bankmachine7.$group_34'.
Found and cleaned up 1 empty switch in `\bankmachine7.$group_18'.
Removing empty process `bankmachine7.$group_18'.
Found and cleaned up 2 empty switches in `\U$$1$62.$group_3'.
Removing empty process `U$$1$62.$group_3'.
Found and cleaned up 2 empty switches in `\U$$1$62.$group_2'.
Removing empty process `U$$1$62.$group_2'.
Found and cleaned up 2 empty switches in `\U$$1$62.$group_1'.
Removing empty process `U$$1$62.$group_1'.
Found and cleaned up 2 empty switches in `\U$$1$62.$group_0'.
Removing empty process `U$$1$62.$group_0'.
Found and cleaned up 2 empty switches in `\fifo$61.$group_10'.
Removing empty process `fifo$61.$group_10'.
Found and cleaned up 2 empty switches in `\fifo$61.$group_7'.
Removing empty process `fifo$61.$group_7'.
Found and cleaned up 3 empty switches in `\fifo$61.$group_11'.
Removing empty process `fifo$61.$group_11'.
Found and cleaned up 3 empty switches in `\trascon$59.$group_1'.
Removing empty process `trascon$59.$group_1'.
Found and cleaned up 2 empty switches in `\trascon$59.$group_0'.
Removing empty process `trascon$59.$group_0'.
Found and cleaned up 3 empty switches in `\trccon$58.$group_1'.
Removing empty process `trccon$58.$group_1'.
Found and cleaned up 2 empty switches in `\trccon$58.$group_0'.
Removing empty process `trccon$58.$group_0'.
Found and cleaned up 3 empty switches in `\twtpcon$57.$group_1'.
Removing empty process `twtpcon$57.$group_1'.
Found and cleaned up 2 empty switches in `\twtpcon$57.$group_0'.
Removing empty process `twtpcon$57.$group_0'.
Found and cleaned up 4 empty switches in `\bankmachine6.$group_33'.
Removing empty process `bankmachine6.$group_33'.
Found and cleaned up 2 empty switches in `\bankmachine6.$group_16'.
Removing empty process `bankmachine6.$group_16'.
Found and cleaned up 2 empty switches in `\bankmachine6.$group_15'.
Removing empty process `bankmachine6.$group_15'.
Found and cleaned up 1 empty switch in `\bankmachine6.$group_32'.
Removing empty process `bankmachine6.$group_32'.
Found and cleaned up 5 empty switches in `\bankmachine6.$group_31'.
Removing empty process `bankmachine6.$group_31'.
Found and cleaned up 5 empty switches in `\bankmachine6.$group_30'.
Removing empty process `bankmachine6.$group_30'.
Found and cleaned up 7 empty switches in `\bankmachine6.$group_29'.
Removing empty process `bankmachine6.$group_29'.
Found and cleaned up 5 empty switches in `\bankmachine6.$group_28'.
Removing empty process `bankmachine6.$group_28'.
Found and cleaned up 5 empty switches in `\bankmachine6.$group_27'.
Removing empty process `bankmachine6.$group_27'.
Found and cleaned up 4 empty switches in `\bankmachine6.$group_26'.
Removing empty process `bankmachine6.$group_26'.
Found and cleaned up 7 empty switches in `\bankmachine6.$group_25'.
Removing empty process `bankmachine6.$group_25'.
Found and cleaned up 15 empty switches in `\bankmachine6.$group_24'.
Removing empty process `bankmachine6.$group_24'.
Found and cleaned up 2 empty switches in `\bankmachine6.$group_23'.
Removing empty process `bankmachine6.$group_23'.
Found and cleaned up 2 empty switches in `\bankmachine6.$group_37'.
Removing empty process `bankmachine6.$group_37'.
Found and cleaned up 2 empty switches in `\bankmachine6.$group_36'.
Removing empty process `bankmachine6.$group_36'.
Found and cleaned up 2 empty switches in `\bankmachine6.$group_35'.
Removing empty process `bankmachine6.$group_35'.
Found and cleaned up 4 empty switches in `\bankmachine6.$group_34'.
Removing empty process `bankmachine6.$group_34'.
Found and cleaned up 1 empty switch in `\bankmachine6.$group_18'.
Removing empty process `bankmachine6.$group_18'.
Found and cleaned up 2 empty switches in `\U$$1$54.$group_3'.
Removing empty process `U$$1$54.$group_3'.
Found and cleaned up 2 empty switches in `\U$$1$54.$group_2'.
Removing empty process `U$$1$54.$group_2'.
Found and cleaned up 2 empty switches in `\U$$1$54.$group_1'.
Removing empty process `U$$1$54.$group_1'.
Found and cleaned up 2 empty switches in `\U$$1$54.$group_0'.
Removing empty process `U$$1$54.$group_0'.
Found and cleaned up 2 empty switches in `\fifo$53.$group_10'.
Removing empty process `fifo$53.$group_10'.
Found and cleaned up 2 empty switches in `\fifo$53.$group_7'.
Removing empty process `fifo$53.$group_7'.
Found and cleaned up 3 empty switches in `\fifo$53.$group_11'.
Removing empty process `fifo$53.$group_11'.
Found and cleaned up 3 empty switches in `\trascon$51.$group_1'.
Removing empty process `trascon$51.$group_1'.
Found and cleaned up 2 empty switches in `\trascon$51.$group_0'.
Removing empty process `trascon$51.$group_0'.
Found and cleaned up 3 empty switches in `\trccon$50.$group_1'.
Removing empty process `trccon$50.$group_1'.
Found and cleaned up 2 empty switches in `\trccon$50.$group_0'.
Removing empty process `trccon$50.$group_0'.
Found and cleaned up 3 empty switches in `\twtpcon$49.$group_1'.
Removing empty process `twtpcon$49.$group_1'.
Found and cleaned up 2 empty switches in `\twtpcon$49.$group_0'.
Removing empty process `twtpcon$49.$group_0'.
Found and cleaned up 4 empty switches in `\bankmachine5.$group_33'.
Removing empty process `bankmachine5.$group_33'.
Found and cleaned up 2 empty switches in `\bankmachine5.$group_16'.
Removing empty process `bankmachine5.$group_16'.
Found and cleaned up 2 empty switches in `\bankmachine5.$group_15'.
Removing empty process `bankmachine5.$group_15'.
Found and cleaned up 1 empty switch in `\bankmachine5.$group_32'.
Removing empty process `bankmachine5.$group_32'.
Found and cleaned up 5 empty switches in `\bankmachine5.$group_31'.
Removing empty process `bankmachine5.$group_31'.
Found and cleaned up 5 empty switches in `\bankmachine5.$group_30'.
Removing empty process `bankmachine5.$group_30'.
Found and cleaned up 7 empty switches in `\bankmachine5.$group_29'.
Removing empty process `bankmachine5.$group_29'.
Found and cleaned up 5 empty switches in `\bankmachine5.$group_28'.
Removing empty process `bankmachine5.$group_28'.
Found and cleaned up 5 empty switches in `\bankmachine5.$group_27'.
Removing empty process `bankmachine5.$group_27'.
Found and cleaned up 4 empty switches in `\bankmachine5.$group_26'.
Removing empty process `bankmachine5.$group_26'.
Found and cleaned up 7 empty switches in `\bankmachine5.$group_25'.
Removing empty process `bankmachine5.$group_25'.
Found and cleaned up 15 empty switches in `\bankmachine5.$group_24'.
Removing empty process `bankmachine5.$group_24'.
Found and cleaned up 2 empty switches in `\bankmachine5.$group_23'.
Removing empty process `bankmachine5.$group_23'.
Found and cleaned up 2 empty switches in `\bankmachine5.$group_37'.
Removing empty process `bankmachine5.$group_37'.
Found and cleaned up 2 empty switches in `\bankmachine5.$group_36'.
Removing empty process `bankmachine5.$group_36'.
Found and cleaned up 2 empty switches in `\bankmachine5.$group_35'.
Removing empty process `bankmachine5.$group_35'.
Found and cleaned up 4 empty switches in `\bankmachine5.$group_34'.
Removing empty process `bankmachine5.$group_34'.
Found and cleaned up 1 empty switch in `\bankmachine5.$group_18'.
Removing empty process `bankmachine5.$group_18'.
Found and cleaned up 2 empty switches in `\U$$1$46.$group_3'.
Removing empty process `U$$1$46.$group_3'.
Found and cleaned up 2 empty switches in `\U$$1$46.$group_2'.
Removing empty process `U$$1$46.$group_2'.
Found and cleaned up 2 empty switches in `\U$$1$46.$group_1'.
Removing empty process `U$$1$46.$group_1'.
Found and cleaned up 2 empty switches in `\U$$1$46.$group_0'.
Removing empty process `U$$1$46.$group_0'.
Found and cleaned up 2 empty switches in `\fifo$45.$group_10'.
Removing empty process `fifo$45.$group_10'.
Found and cleaned up 2 empty switches in `\fifo$45.$group_7'.
Removing empty process `fifo$45.$group_7'.
Found and cleaned up 3 empty switches in `\fifo$45.$group_11'.
Removing empty process `fifo$45.$group_11'.
Found and cleaned up 3 empty switches in `\trascon$43.$group_1'.
Removing empty process `trascon$43.$group_1'.
Found and cleaned up 2 empty switches in `\trascon$43.$group_0'.
Removing empty process `trascon$43.$group_0'.
Found and cleaned up 3 empty switches in `\trccon$42.$group_1'.
Removing empty process `trccon$42.$group_1'.
Found and cleaned up 2 empty switches in `\trccon$42.$group_0'.
Removing empty process `trccon$42.$group_0'.
Found and cleaned up 3 empty switches in `\twtpcon$41.$group_1'.
Removing empty process `twtpcon$41.$group_1'.
Found and cleaned up 2 empty switches in `\twtpcon$41.$group_0'.
Removing empty process `twtpcon$41.$group_0'.
Found and cleaned up 4 empty switches in `\bankmachine4.$group_33'.
Removing empty process `bankmachine4.$group_33'.
Found and cleaned up 2 empty switches in `\bankmachine4.$group_16'.
Removing empty process `bankmachine4.$group_16'.
Found and cleaned up 2 empty switches in `\bankmachine4.$group_15'.
Removing empty process `bankmachine4.$group_15'.
Found and cleaned up 1 empty switch in `\bankmachine4.$group_32'.
Removing empty process `bankmachine4.$group_32'.
Found and cleaned up 5 empty switches in `\bankmachine4.$group_31'.
Removing empty process `bankmachine4.$group_31'.
Found and cleaned up 5 empty switches in `\bankmachine4.$group_30'.
Removing empty process `bankmachine4.$group_30'.
Found and cleaned up 7 empty switches in `\bankmachine4.$group_29'.
Removing empty process `bankmachine4.$group_29'.
Found and cleaned up 5 empty switches in `\bankmachine4.$group_28'.
Removing empty process `bankmachine4.$group_28'.
Found and cleaned up 5 empty switches in `\bankmachine4.$group_27'.
Removing empty process `bankmachine4.$group_27'.
Found and cleaned up 4 empty switches in `\bankmachine4.$group_26'.
Removing empty process `bankmachine4.$group_26'.
Found and cleaned up 7 empty switches in `\bankmachine4.$group_25'.
Removing empty process `bankmachine4.$group_25'.
Found and cleaned up 15 empty switches in `\bankmachine4.$group_24'.
Removing empty process `bankmachine4.$group_24'.
Found and cleaned up 2 empty switches in `\bankmachine4.$group_23'.
Removing empty process `bankmachine4.$group_23'.
Found and cleaned up 2 empty switches in `\bankmachine4.$group_37'.
Removing empty process `bankmachine4.$group_37'.
Found and cleaned up 2 empty switches in `\bankmachine4.$group_36'.
Removing empty process `bankmachine4.$group_36'.
Found and cleaned up 2 empty switches in `\bankmachine4.$group_35'.
Removing empty process `bankmachine4.$group_35'.
Found and cleaned up 4 empty switches in `\bankmachine4.$group_34'.
Removing empty process `bankmachine4.$group_34'.
Found and cleaned up 1 empty switch in `\bankmachine4.$group_18'.
Removing empty process `bankmachine4.$group_18'.
Found and cleaned up 2 empty switches in `\U$$1$38.$group_3'.
Removing empty process `U$$1$38.$group_3'.
Found and cleaned up 2 empty switches in `\U$$1$38.$group_2'.
Removing empty process `U$$1$38.$group_2'.
Found and cleaned up 2 empty switches in `\U$$1$38.$group_1'.
Removing empty process `U$$1$38.$group_1'.
Found and cleaned up 2 empty switches in `\U$$1$38.$group_0'.
Removing empty process `U$$1$38.$group_0'.
Found and cleaned up 2 empty switches in `\fifo$37.$group_10'.
Removing empty process `fifo$37.$group_10'.
Found and cleaned up 2 empty switches in `\fifo$37.$group_7'.
Removing empty process `fifo$37.$group_7'.
Found and cleaned up 3 empty switches in `\fifo$37.$group_11'.
Removing empty process `fifo$37.$group_11'.
Found and cleaned up 3 empty switches in `\trascon$35.$group_1'.
Removing empty process `trascon$35.$group_1'.
Found and cleaned up 2 empty switches in `\trascon$35.$group_0'.
Removing empty process `trascon$35.$group_0'.
Found and cleaned up 3 empty switches in `\trccon$34.$group_1'.
Removing empty process `trccon$34.$group_1'.
Found and cleaned up 2 empty switches in `\trccon$34.$group_0'.
Removing empty process `trccon$34.$group_0'.
Found and cleaned up 3 empty switches in `\twtpcon$33.$group_1'.
Removing empty process `twtpcon$33.$group_1'.
Found and cleaned up 2 empty switches in `\twtpcon$33.$group_0'.
Removing empty process `twtpcon$33.$group_0'.
Found and cleaned up 4 empty switches in `\bankmachine3.$group_33'.
Removing empty process `bankmachine3.$group_33'.
Found and cleaned up 2 empty switches in `\bankmachine3.$group_16'.
Removing empty process `bankmachine3.$group_16'.
Found and cleaned up 2 empty switches in `\bankmachine3.$group_15'.
Removing empty process `bankmachine3.$group_15'.
Found and cleaned up 1 empty switch in `\bankmachine3.$group_32'.
Removing empty process `bankmachine3.$group_32'.
Found and cleaned up 5 empty switches in `\bankmachine3.$group_31'.
Removing empty process `bankmachine3.$group_31'.
Found and cleaned up 5 empty switches in `\bankmachine3.$group_30'.
Removing empty process `bankmachine3.$group_30'.
Found and cleaned up 7 empty switches in `\bankmachine3.$group_29'.
Removing empty process `bankmachine3.$group_29'.
Found and cleaned up 5 empty switches in `\bankmachine3.$group_28'.
Removing empty process `bankmachine3.$group_28'.
Found and cleaned up 5 empty switches in `\bankmachine3.$group_27'.
Removing empty process `bankmachine3.$group_27'.
Found and cleaned up 4 empty switches in `\bankmachine3.$group_26'.
Removing empty process `bankmachine3.$group_26'.
Found and cleaned up 7 empty switches in `\bankmachine3.$group_25'.
Removing empty process `bankmachine3.$group_25'.
Found and cleaned up 15 empty switches in `\bankmachine3.$group_24'.
Removing empty process `bankmachine3.$group_24'.
Found and cleaned up 2 empty switches in `\bankmachine3.$group_23'.
Removing empty process `bankmachine3.$group_23'.
Found and cleaned up 2 empty switches in `\bankmachine3.$group_37'.
Removing empty process `bankmachine3.$group_37'.
Found and cleaned up 2 empty switches in `\bankmachine3.$group_36'.
Removing empty process `bankmachine3.$group_36'.
Found and cleaned up 2 empty switches in `\bankmachine3.$group_35'.
Removing empty process `bankmachine3.$group_35'.
Found and cleaned up 4 empty switches in `\bankmachine3.$group_34'.
Removing empty process `bankmachine3.$group_34'.
Found and cleaned up 1 empty switch in `\bankmachine3.$group_18'.
Removing empty process `bankmachine3.$group_18'.
Found and cleaned up 2 empty switches in `\U$$1$30.$group_3'.
Removing empty process `U$$1$30.$group_3'.
Found and cleaned up 2 empty switches in `\U$$1$30.$group_2'.
Removing empty process `U$$1$30.$group_2'.
Found and cleaned up 2 empty switches in `\U$$1$30.$group_1'.
Removing empty process `U$$1$30.$group_1'.
Found and cleaned up 2 empty switches in `\U$$1$30.$group_0'.
Removing empty process `U$$1$30.$group_0'.
Found and cleaned up 2 empty switches in `\fifo$29.$group_10'.
Removing empty process `fifo$29.$group_10'.
Found and cleaned up 2 empty switches in `\fifo$29.$group_7'.
Removing empty process `fifo$29.$group_7'.
Found and cleaned up 3 empty switches in `\fifo$29.$group_11'.
Removing empty process `fifo$29.$group_11'.
Found and cleaned up 3 empty switches in `\trascon$27.$group_1'.
Removing empty process `trascon$27.$group_1'.
Found and cleaned up 2 empty switches in `\trascon$27.$group_0'.
Removing empty process `trascon$27.$group_0'.
Found and cleaned up 3 empty switches in `\trccon$26.$group_1'.
Removing empty process `trccon$26.$group_1'.
Found and cleaned up 2 empty switches in `\trccon$26.$group_0'.
Removing empty process `trccon$26.$group_0'.
Found and cleaned up 3 empty switches in `\twtpcon$25.$group_1'.
Removing empty process `twtpcon$25.$group_1'.
Found and cleaned up 2 empty switches in `\twtpcon$25.$group_0'.
Removing empty process `twtpcon$25.$group_0'.
Found and cleaned up 4 empty switches in `\bankmachine2.$group_33'.
Removing empty process `bankmachine2.$group_33'.
Found and cleaned up 2 empty switches in `\bankmachine2.$group_16'.
Removing empty process `bankmachine2.$group_16'.
Found and cleaned up 2 empty switches in `\bankmachine2.$group_15'.
Removing empty process `bankmachine2.$group_15'.
Found and cleaned up 1 empty switch in `\bankmachine2.$group_32'.
Removing empty process `bankmachine2.$group_32'.
Found and cleaned up 5 empty switches in `\bankmachine2.$group_31'.
Removing empty process `bankmachine2.$group_31'.
Found and cleaned up 5 empty switches in `\bankmachine2.$group_30'.
Removing empty process `bankmachine2.$group_30'.
Found and cleaned up 7 empty switches in `\bankmachine2.$group_29'.
Removing empty process `bankmachine2.$group_29'.
Found and cleaned up 5 empty switches in `\bankmachine2.$group_28'.
Removing empty process `bankmachine2.$group_28'.
Found and cleaned up 5 empty switches in `\bankmachine2.$group_27'.
Removing empty process `bankmachine2.$group_27'.
Found and cleaned up 4 empty switches in `\bankmachine2.$group_26'.
Removing empty process `bankmachine2.$group_26'.
Found and cleaned up 7 empty switches in `\bankmachine2.$group_25'.
Removing empty process `bankmachine2.$group_25'.
Found and cleaned up 15 empty switches in `\bankmachine2.$group_24'.
Removing empty process `bankmachine2.$group_24'.
Found and cleaned up 2 empty switches in `\bankmachine2.$group_23'.
Removing empty process `bankmachine2.$group_23'.
Found and cleaned up 2 empty switches in `\bankmachine2.$group_37'.
Removing empty process `bankmachine2.$group_37'.
Found and cleaned up 2 empty switches in `\bankmachine2.$group_36'.
Removing empty process `bankmachine2.$group_36'.
Found and cleaned up 2 empty switches in `\bankmachine2.$group_35'.
Removing empty process `bankmachine2.$group_35'.
Found and cleaned up 4 empty switches in `\bankmachine2.$group_34'.
Removing empty process `bankmachine2.$group_34'.
Found and cleaned up 1 empty switch in `\bankmachine2.$group_18'.
Removing empty process `bankmachine2.$group_18'.
Found and cleaned up 2 empty switches in `\U$$1$22.$group_3'.
Removing empty process `U$$1$22.$group_3'.
Found and cleaned up 2 empty switches in `\U$$1$22.$group_2'.
Removing empty process `U$$1$22.$group_2'.
Found and cleaned up 2 empty switches in `\U$$1$22.$group_1'.
Removing empty process `U$$1$22.$group_1'.
Found and cleaned up 2 empty switches in `\U$$1$22.$group_0'.
Removing empty process `U$$1$22.$group_0'.
Found and cleaned up 2 empty switches in `\fifo$21.$group_10'.
Removing empty process `fifo$21.$group_10'.
Found and cleaned up 2 empty switches in `\fifo$21.$group_7'.
Removing empty process `fifo$21.$group_7'.
Found and cleaned up 3 empty switches in `\fifo$21.$group_11'.
Removing empty process `fifo$21.$group_11'.
Found and cleaned up 3 empty switches in `\trascon$19.$group_1'.
Removing empty process `trascon$19.$group_1'.
Found and cleaned up 2 empty switches in `\trascon$19.$group_0'.
Removing empty process `trascon$19.$group_0'.
Found and cleaned up 3 empty switches in `\trccon$18.$group_1'.
Removing empty process `trccon$18.$group_1'.
Found and cleaned up 2 empty switches in `\trccon$18.$group_0'.
Removing empty process `trccon$18.$group_0'.
Found and cleaned up 3 empty switches in `\twtpcon$17.$group_1'.
Removing empty process `twtpcon$17.$group_1'.
Found and cleaned up 2 empty switches in `\twtpcon$17.$group_0'.
Removing empty process `twtpcon$17.$group_0'.
Found and cleaned up 4 empty switches in `\bankmachine1.$group_33'.
Removing empty process `bankmachine1.$group_33'.
Found and cleaned up 2 empty switches in `\bankmachine1.$group_16'.
Removing empty process `bankmachine1.$group_16'.
Found and cleaned up 2 empty switches in `\bankmachine1.$group_15'.
Removing empty process `bankmachine1.$group_15'.
Found and cleaned up 1 empty switch in `\bankmachine1.$group_32'.
Removing empty process `bankmachine1.$group_32'.
Found and cleaned up 5 empty switches in `\bankmachine1.$group_31'.
Removing empty process `bankmachine1.$group_31'.
Found and cleaned up 5 empty switches in `\bankmachine1.$group_30'.
Removing empty process `bankmachine1.$group_30'.
Found and cleaned up 7 empty switches in `\bankmachine1.$group_29'.
Removing empty process `bankmachine1.$group_29'.
Found and cleaned up 5 empty switches in `\bankmachine1.$group_28'.
Removing empty process `bankmachine1.$group_28'.
Found and cleaned up 5 empty switches in `\bankmachine1.$group_27'.
Removing empty process `bankmachine1.$group_27'.
Found and cleaned up 4 empty switches in `\bankmachine1.$group_26'.
Removing empty process `bankmachine1.$group_26'.
Found and cleaned up 7 empty switches in `\bankmachine1.$group_25'.
Removing empty process `bankmachine1.$group_25'.
Found and cleaned up 15 empty switches in `\bankmachine1.$group_24'.
Removing empty process `bankmachine1.$group_24'.
Found and cleaned up 2 empty switches in `\bankmachine1.$group_23'.
Removing empty process `bankmachine1.$group_23'.
Found and cleaned up 2 empty switches in `\bankmachine1.$group_37'.
Removing empty process `bankmachine1.$group_37'.
Found and cleaned up 2 empty switches in `\bankmachine1.$group_36'.
Removing empty process `bankmachine1.$group_36'.
Found and cleaned up 2 empty switches in `\bankmachine1.$group_35'.
Removing empty process `bankmachine1.$group_35'.
Found and cleaned up 4 empty switches in `\bankmachine1.$group_34'.
Removing empty process `bankmachine1.$group_34'.
Found and cleaned up 1 empty switch in `\bankmachine1.$group_18'.
Removing empty process `bankmachine1.$group_18'.
Found and cleaned up 2 empty switches in `\U$$1$14.$group_3'.
Removing empty process `U$$1$14.$group_3'.
Found and cleaned up 2 empty switches in `\U$$1$14.$group_2'.
Removing empty process `U$$1$14.$group_2'.
Found and cleaned up 2 empty switches in `\U$$1$14.$group_1'.
Removing empty process `U$$1$14.$group_1'.
Found and cleaned up 2 empty switches in `\U$$1$14.$group_0'.
Removing empty process `U$$1$14.$group_0'.
Found and cleaned up 2 empty switches in `\fifo$13.$group_10'.
Removing empty process `fifo$13.$group_10'.
Found and cleaned up 2 empty switches in `\fifo$13.$group_7'.
Removing empty process `fifo$13.$group_7'.
Found and cleaned up 3 empty switches in `\fifo$13.$group_11'.
Removing empty process `fifo$13.$group_11'.
Found and cleaned up 3 empty switches in `\trascon$11.$group_1'.
Removing empty process `trascon$11.$group_1'.
Found and cleaned up 2 empty switches in `\trascon$11.$group_0'.
Removing empty process `trascon$11.$group_0'.
Found and cleaned up 3 empty switches in `\trccon$10.$group_1'.
Removing empty process `trccon$10.$group_1'.
Found and cleaned up 2 empty switches in `\trccon$10.$group_0'.
Removing empty process `trccon$10.$group_0'.
Found and cleaned up 3 empty switches in `\twtpcon$9.$group_1'.
Removing empty process `twtpcon$9.$group_1'.
Found and cleaned up 2 empty switches in `\twtpcon$9.$group_0'.
Removing empty process `twtpcon$9.$group_0'.
Found and cleaned up 4 empty switches in `\bankmachine0.$group_33'.
Removing empty process `bankmachine0.$group_33'.
Found and cleaned up 2 empty switches in `\bankmachine0.$group_16'.
Removing empty process `bankmachine0.$group_16'.
Found and cleaned up 2 empty switches in `\bankmachine0.$group_15'.
Removing empty process `bankmachine0.$group_15'.
Found and cleaned up 1 empty switch in `\bankmachine0.$group_32'.
Removing empty process `bankmachine0.$group_32'.
Found and cleaned up 5 empty switches in `\bankmachine0.$group_31'.
Removing empty process `bankmachine0.$group_31'.
Found and cleaned up 5 empty switches in `\bankmachine0.$group_30'.
Removing empty process `bankmachine0.$group_30'.
Found and cleaned up 7 empty switches in `\bankmachine0.$group_29'.
Removing empty process `bankmachine0.$group_29'.
Found and cleaned up 5 empty switches in `\bankmachine0.$group_28'.
Removing empty process `bankmachine0.$group_28'.
Found and cleaned up 5 empty switches in `\bankmachine0.$group_27'.
Removing empty process `bankmachine0.$group_27'.
Found and cleaned up 4 empty switches in `\bankmachine0.$group_26'.
Removing empty process `bankmachine0.$group_26'.
Found and cleaned up 7 empty switches in `\bankmachine0.$group_25'.
Removing empty process `bankmachine0.$group_25'.
Found and cleaned up 15 empty switches in `\bankmachine0.$group_24'.
Removing empty process `bankmachine0.$group_24'.
Found and cleaned up 2 empty switches in `\bankmachine0.$group_23'.
Removing empty process `bankmachine0.$group_23'.
Found and cleaned up 2 empty switches in `\bankmachine0.$group_37'.
Removing empty process `bankmachine0.$group_37'.
Found and cleaned up 2 empty switches in `\bankmachine0.$group_36'.
Removing empty process `bankmachine0.$group_36'.
Found and cleaned up 2 empty switches in `\bankmachine0.$group_35'.
Removing empty process `bankmachine0.$group_35'.
Found and cleaned up 4 empty switches in `\bankmachine0.$group_34'.
Removing empty process `bankmachine0.$group_34'.
Found and cleaned up 1 empty switch in `\bankmachine0.$group_18'.
Removing empty process `bankmachine0.$group_18'.
Found and cleaned up 2 empty switches in `\U$$1$6.$group_3'.
Removing empty process `U$$1$6.$group_3'.
Found and cleaned up 2 empty switches in `\U$$1$6.$group_2'.
Removing empty process `U$$1$6.$group_2'.
Found and cleaned up 2 empty switches in `\U$$1$6.$group_1'.
Removing empty process `U$$1$6.$group_1'.
Found and cleaned up 2 empty switches in `\U$$1$6.$group_0'.
Removing empty process `U$$1$6.$group_0'.
Found and cleaned up 2 empty switches in `\fifo.$group_10'.
Removing empty process `fifo.$group_10'.
Found and cleaned up 2 empty switches in `\fifo.$group_7'.
Removing empty process `fifo.$group_7'.
Found and cleaned up 3 empty switches in `\fifo.$group_11'.
Removing empty process `fifo.$group_11'.
Found and cleaned up 3 empty switches in `\trascon.$group_1'.
Removing empty process `trascon.$group_1'.
Found and cleaned up 2 empty switches in `\trascon.$group_0'.
Removing empty process `trascon.$group_0'.
Found and cleaned up 3 empty switches in `\trccon.$group_1'.
Removing empty process `trccon.$group_1'.
Found and cleaned up 2 empty switches in `\trccon.$group_0'.
Removing empty process `trccon.$group_0'.
Found and cleaned up 3 empty switches in `\twtpcon.$group_1'.
Removing empty process `twtpcon.$group_1'.
Found and cleaned up 2 empty switches in `\twtpcon.$group_0'.
Removing empty process `twtpcon.$group_0'.
Found and cleaned up 7 empty switches in `\refresher.$group_4'.
Removing empty process `refresher.$group_4'.
Found and cleaned up 4 empty switches in `\refresher.$group_8'.
Removing empty process `refresher.$group_8'.
Found and cleaned up 3 empty switches in `\refresher.$group_7'.
Removing empty process `refresher.$group_7'.
Found and cleaned up 2 empty switches in `\refresher.$group_6'.
Removing empty process `refresher.$group_6'.
Found and cleaned up 1 empty switch in `\refresher.$group_5'.
Removing empty process `refresher.$group_5'.
Found and cleaned up 4 empty switches in `\timeline$5.$group_6'.
Removing empty process `timeline$5.$group_6'.
Found and cleaned up 4 empty switches in `\timeline$5.$group_5'.
Removing empty process `timeline$5.$group_5'.
Found and cleaned up 4 empty switches in `\timeline$5.$group_4'.
Removing empty process `timeline$5.$group_4'.
Found and cleaned up 4 empty switches in `\timeline$5.$group_3'.
Removing empty process `timeline$5.$group_3'.
Found and cleaned up 4 empty switches in `\timeline$5.$group_2'.
Removing empty process `timeline$5.$group_2'.
Found and cleaned up 4 empty switches in `\timeline$5.$group_1'.
Removing empty process `timeline$5.$group_1'.
Found and cleaned up 3 empty switches in `\timeline$5.$group_0'.
Removing empty process `timeline$5.$group_0'.
Found and cleaned up 3 empty switches in `\zqcs_timer.$group_1'.
Removing empty process `zqcs_timer.$group_1'.
Found and cleaned up 2 empty switches in `\zqcs_timer.$group_0'.
Removing empty process `zqcs_timer.$group_0'.
Found and cleaned up 3 empty switches in `\sequencer.$group_5'.
Removing empty process `sequencer.$group_5'.
Found and cleaned up 3 empty switches in `\sequencer.$group_7'.
Removing empty process `sequencer.$group_7'.
Found and cleaned up 3 empty switches in `\sequencer.$group_6'.
Removing empty process `sequencer.$group_6'.
Found and cleaned up 2 empty switches in `\timeline.$group_6'.
Removing empty process `timeline.$group_6'.
Found and cleaned up 4 empty switches in `\timeline.$group_5'.
Removing empty process `timeline.$group_5'.
Found and cleaned up 4 empty switches in `\timeline.$group_4'.
Removing empty process `timeline.$group_4'.
Found and cleaned up 4 empty switches in `\timeline.$group_3'.
Removing empty process `timeline.$group_3'.
Found and cleaned up 4 empty switches in `\timeline.$group_2'.
Removing empty process `timeline.$group_2'.
Found and cleaned up 4 empty switches in `\timeline.$group_1'.
Removing empty process `timeline.$group_1'.
Found and cleaned up 3 empty switches in `\timeline.$group_0'.
Removing empty process `timeline.$group_0'.
Found and cleaned up 3 empty switches in `\postponer.$group_1'.
Removing empty process `postponer.$group_1'.
Found and cleaned up 3 empty switches in `\postponer.$group_0'.
Removing empty process `postponer.$group_0'.
Found and cleaned up 3 empty switches in `\timer.$group_1'.
Removing empty process `timer.$group_1'.
Found and cleaned up 2 empty switches in `\timer.$group_0'.
Removing empty process `timer.$group_0'.
Found and cleaned up 1 empty switch in `\dfii.$group_35'.
Removing empty process `dfii.$group_35'.
Found and cleaned up 1 empty switch in `\dfii.$group_34'.
Removing empty process `dfii.$group_34'.
Found and cleaned up 1 empty switch in `\dfii.$group_33'.
Removing empty process `dfii.$group_33'.
Found and cleaned up 1 empty switch in `\dfii.$group_32'.
Removing empty process `dfii.$group_32'.
Found and cleaned up 1 empty switch in `\dfii.$group_31'.
Removing empty process `dfii.$group_31'.
Found and cleaned up 1 empty switch in `\dfii.$group_30'.
Removing empty process `dfii.$group_30'.
Found and cleaned up 1 empty switch in `\dfii.$group_29'.
Removing empty process `dfii.$group_29'.
Found and cleaned up 1 empty switch in `\dfii.$group_28'.
Removing empty process `dfii.$group_28'.
Found and cleaned up 1 empty switch in `\dfii.$group_27'.
Removing empty process `dfii.$group_27'.
Found and cleaned up 1 empty switch in `\dfii.$group_26'.
Removing empty process `dfii.$group_26'.
Found and cleaned up 1 empty switch in `\dfii.$group_25'.
Removing empty process `dfii.$group_25'.
Found and cleaned up 1 empty switch in `\dfii.$group_24'.
Removing empty process `dfii.$group_24'.
Found and cleaned up 1 empty switch in `\dfii.$group_23'.
Removing empty process `dfii.$group_23'.
Found and cleaned up 1 empty switch in `\dfii.$group_22'.
Removing empty process `dfii.$group_22'.
Found and cleaned up 1 empty switch in `\dfii.$group_21'.
Removing empty process `dfii.$group_21'.
Found and cleaned up 1 empty switch in `\dfii.$group_20'.
Removing empty process `dfii.$group_20'.
Found and cleaned up 1 empty switch in `\dfii.$group_19'.
Removing empty process `dfii.$group_19'.
Found and cleaned up 1 empty switch in `\dfii.$group_18'.
Removing empty process `dfii.$group_18'.
Found and cleaned up 1 empty switch in `\dfii.$group_17'.
Removing empty process `dfii.$group_17'.
Found and cleaned up 1 empty switch in `\dfii.$group_16'.
Removing empty process `dfii.$group_16'.
Found and cleaned up 1 empty switch in `\dfii.$group_15'.
Removing empty process `dfii.$group_15'.
Found and cleaned up 1 empty switch in `\dfii.$group_14'.
Removing empty process `dfii.$group_14'.
Found and cleaned up 1 empty switch in `\dfii.$group_13'.
Removing empty process `dfii.$group_13'.
Found and cleaned up 1 empty switch in `\dfii.$group_12'.
Removing empty process `dfii.$group_12'.
Found and cleaned up 1 empty switch in `\dfii.$group_11'.
Removing empty process `dfii.$group_11'.
Found and cleaned up 1 empty switch in `\dfii.$group_10'.
Removing empty process `dfii.$group_10'.
Found and cleaned up 1 empty switch in `\dfii.$group_9'.
Removing empty process `dfii.$group_9'.
Found and cleaned up 1 empty switch in `\dfii.$group_8'.
Removing empty process `dfii.$group_8'.
Found and cleaned up 1 empty switch in `\dfii.$group_7'.
Removing empty process `dfii.$group_7'.
Found and cleaned up 1 empty switch in `\dfii.$group_6'.
Removing empty process `dfii.$group_6'.
Found and cleaned up 1 empty switch in `\dfii.$group_5'.
Removing empty process `dfii.$group_5'.
Found and cleaned up 1 empty switch in `\dfii.$group_4'.
Removing empty process `dfii.$group_4'.
Found and cleaned up 1 empty switch in `\dfii.$group_3'.
Removing empty process `dfii.$group_3'.
Found and cleaned up 1 empty switch in `\dfii.$group_2'.
Removing empty process `dfii.$group_2'.
Found and cleaned up 1 empty switch in `\dfii.$group_1'.
Removing empty process `dfii.$group_1'.
Found and cleaned up 1 empty switch in `\dfii.$group_0'.
Removing empty process `dfii.$group_0'.
Found and cleaned up 1 empty switch in `\phase_1.$group_9'.
Removing empty process `phase_1.$group_9'.
Found and cleaned up 1 empty switch in `\phase_1.$group_8'.
Removing empty process `phase_1.$group_8'.
Found and cleaned up 1 empty switch in `\phase_1.$group_7'.
Removing empty process `phase_1.$group_7'.
Found and cleaned up 1 empty switch in `\phase_1.$group_6'.
Removing empty process `phase_1.$group_6'.
Found and cleaned up 2 empty switches in `\phase_1.$group_10'.
Removing empty process `phase_1.$group_10'.
Found and cleaned up 1 empty switch in `\phase_0.$group_9'.
Removing empty process `phase_0.$group_9'.
Found and cleaned up 1 empty switch in `\phase_0.$group_8'.
Removing empty process `phase_0.$group_8'.
Found and cleaned up 1 empty switch in `\phase_0.$group_7'.
Removing empty process `phase_0.$group_7'.
Found and cleaned up 1 empty switch in `\phase_0.$group_6'.
Removing empty process `phase_0.$group_6'.
Found and cleaned up 2 empty switches in `\phase_0.$group_10'.
Removing empty process `phase_0.$group_10'.
Found and cleaned up 1 empty switch in `\wb_decoder$4.$group_5'.
Removing empty process `wb_decoder$4.$group_5'.
Found and cleaned up 1 empty switch in `\wb_decoder$4.$group_6'.
Removing empty process `wb_decoder$4.$group_6'.
Found and cleaned up 4 empty switches in `\csr_bridge_0$3.$group_5'.
Removing empty process `csr_bridge_0$3.$group_5'.
Found and cleaned up 2 empty switches in `\csr_bridge_0$3.$group_4'.
Removing empty process `csr_bridge_0$3.$group_4'.
Found and cleaned up 2 empty switches in `\csr_bridge_0$3.$group_3'.
Removing empty process `csr_bridge_0$3.$group_3'.
Found and cleaned up 2 empty switches in `\csr_bridge_0$3.$group_2'.
Removing empty process `csr_bridge_0$3.$group_2'.
Found and cleaned up 4 empty switches in `\csr_bridge_0$3.$group_7'.
Removing empty process `csr_bridge_0$3.$group_7'.
Found and cleaned up 3 empty switches in `\csr_bridge_0$3.$group_6'.
Removing empty process `csr_bridge_0$3.$group_6'.
Found and cleaned up 2 empty switches in `\csr_mux_0$2.$group_36'.
Removing empty process `csr_mux_0$2.$group_36'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_26'.
Removing empty process `csr_mux_0$2.$group_26'.
Found and cleaned up 2 empty switches in `\csr_mux_0$2.$group_25'.
Removing empty process `csr_mux_0$2.$group_25'.
Found and cleaned up 10 empty switches in `\csr_mux_0$2.$group_35'.
Removing empty process `csr_mux_0$2.$group_35'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_23'.
Removing empty process `csr_mux_0$2.$group_23'.
Found and cleaned up 2 empty switches in `\csr_mux_0$2.$group_22'.
Removing empty process `csr_mux_0$2.$group_22'.
Found and cleaned up 2 empty switches in `\csr_mux_0$2.$group_34'.
Removing empty process `csr_mux_0$2.$group_34'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_20'.
Removing empty process `csr_mux_0$2.$group_20'.
Found and cleaned up 1 empty switch in `\csr_mux_0$2.$group_19'.
Removing empty process `csr_mux_0$2.$group_19'.
Found and cleaned up 2 empty switches in `\csr_mux_0$2.$group_18'.
Removing empty process `csr_mux_0$2.$group_18'.
Found and cleaned up 10 empty switches in `\csr_mux_0$2.$group_17'.
Removing empty process `csr_mux_0$2.$group_17'.
Found and cleaned up 2 empty switches in `\csr_mux_0$2.$group_16'.
Removing empty process `csr_mux_0$2.$group_16'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_38'.
Removing empty process `csr_mux_0$2.$group_38'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_14'.
Removing empty process `csr_mux_0$2.$group_14'.
Found and cleaned up 2 empty switches in `\csr_mux_0$2.$group_13'.
Removing empty process `csr_mux_0$2.$group_13'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_32'.
Removing empty process `csr_mux_0$2.$group_32'.
Found and cleaned up 4 empty switches in `\csr_mux_0$2.$group_11'.
Removing empty process `csr_mux_0$2.$group_11'.
Found and cleaned up 2 empty switches in `\csr_mux_0$2.$group_10'.
Removing empty process `csr_mux_0$2.$group_10'.
Found and cleaned up 2 empty switches in `\csr_mux_0$2.$group_31'.
Removing empty process `csr_mux_0$2.$group_31'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_8'.
Removing empty process `csr_mux_0$2.$group_8'.
Found and cleaned up 2 empty switches in `\csr_mux_0$2.$group_7'.
Removing empty process `csr_mux_0$2.$group_7'.
Found and cleaned up 1 empty switch in `\csr_mux_0$2.$group_37'.
Removing empty process `csr_mux_0$2.$group_37'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_5'.
Removing empty process `csr_mux_0$2.$group_5'.
Found and cleaned up 2 empty switches in `\csr_mux_0$2.$group_4'.
Removing empty process `csr_mux_0$2.$group_4'.
Found and cleaned up 4 empty switches in `\csr_mux_0$2.$group_29'.
Removing empty process `csr_mux_0$2.$group_29'.
Found and cleaned up 3 empty switches in `\csr_mux_0$2.$group_2'.
Removing empty process `csr_mux_0$2.$group_2'.
Found and cleaned up 2 empty switches in `\csr_mux_0$2.$group_1'.
Removing empty process `csr_mux_0$2.$group_1'.
Found and cleaned up 2 empty switches in `\csr_mux_0$2.$group_28'.
Removing empty process `csr_mux_0$2.$group_28'.
Removing empty process `ddrphy.$group_122'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_89'.
Removing empty process `ddrphy.$group_89'.
Removing empty process `ddrphy.$group_88'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_139'.
Removing empty process `ddrphy.$group_139'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_86'.
Removing empty process `ddrphy.$group_86'.
Removing empty process `ddrphy.$group_85'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_120'.
Removing empty process `ddrphy.$group_120'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_83'.
Removing empty process `ddrphy.$group_83'.
Removing empty process `ddrphy.$group_82'.
Removing empty process `ddrphy.$group_119'.
Found and cleaned up 17 empty switches in `\ddrphy.$group_80'.
Removing empty process `ddrphy.$group_80'.
Found and cleaned up 17 empty switches in `\ddrphy.$group_79'.
Removing empty process `ddrphy.$group_79'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_78'.
Removing empty process `ddrphy.$group_78'.
Removing empty process `ddrphy.$group_77'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_131'.
Removing empty process `ddrphy.$group_131'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_75'.
Removing empty process `ddrphy.$group_75'.
Removing empty process `ddrphy.$group_74'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_117'.
Removing empty process `ddrphy.$group_117'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_72'.
Removing empty process `ddrphy.$group_72'.
Removing empty process `ddrphy.$group_116'.
Removing empty process `ddrphy.$group_145'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_114'.
Removing empty process `ddrphy.$group_114'.
Removing empty process `ddrphy.$group_113'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_129'.
Removing empty process `ddrphy.$group_129'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_111'.
Removing empty process `ddrphy.$group_111'.
Removing empty process `ddrphy.$group_110'.
Removing empty process `ddrphy.$group_128'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_108'.
Removing empty process `ddrphy.$group_108'.
Removing empty process `ddrphy.$group_107'.
Removing empty process `ddrphy.$group_146'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_105'.
Removing empty process `ddrphy.$group_105'.
Removing empty process `ddrphy.$group_104'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_126'.
Removing empty process `ddrphy.$group_126'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_102'.
Removing empty process `ddrphy.$group_102'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_101'.
Removing empty process `ddrphy.$group_101'.
Removing empty process `ddrphy.$group_100'.
Removing empty process `ddrphy.$group_125'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_98'.
Removing empty process `ddrphy.$group_98'.
Removing empty process `ddrphy.$group_97'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_133'.
Removing empty process `ddrphy.$group_133'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_95'.
Removing empty process `ddrphy.$group_95'.
Removing empty process `ddrphy.$group_94'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_123'.
Removing empty process `ddrphy.$group_123'.
Found and cleaned up 1 empty switch in `\ddrphy.$group_92'.
Removing empty process `ddrphy.$group_92'.
Found and cleaned up 3 empty switches in `\ddrphy.$group_1'.
Removing empty process `ddrphy.$group_1'.
Removing empty process `ddrphy.$group_91'.
Found and cleaned up 2 empty switches in `\dqsbufm_manager1.$group_2'.
Removing empty process `dqsbufm_manager1.$group_2'.
Found and cleaned up 3 empty switches in `\dqsbufm_manager1.$group_1'.
Removing empty process `dqsbufm_manager1.$group_1'.
Found and cleaned up 3 empty switches in `\dqsbufm_manager1.$group_0'.
Removing empty process `dqsbufm_manager1.$group_0'.
Found and cleaned up 2 empty switches in `\dqsbufm_manager0.$group_2'.
Removing empty process `dqsbufm_manager0.$group_2'.
Found and cleaned up 3 empty switches in `\dqsbufm_manager0.$group_1'.
Removing empty process `dqsbufm_manager0.$group_1'.
Found and cleaned up 3 empty switches in `\dqsbufm_manager0.$group_0'.
Removing empty process `dqsbufm_manager0.$group_0'.
Found and cleaned up 1 empty switch in `\init.$group_0'.
Removing empty process `init.$group_0'.
Found and cleaned up 3 empty switches in `\U$$2.$group_5'.
Removing empty process `U$$2.$group_5'.
Found and cleaned up 3 empty switches in `\U$$2.$group_4'.
Removing empty process `U$$2.$group_4'.
Found and cleaned up 3 empty switches in `\U$$2.$group_3'.
Removing empty process `U$$2.$group_3'.
Found and cleaned up 3 empty switches in `\U$$2.$group_2'.
Removing empty process `U$$2.$group_2'.
Found and cleaned up 3 empty switches in `\U$$2.$group_1'.
Removing empty process `U$$2.$group_1'.
Found and cleaned up 3 empty switches in `\U$$2.$group_0'.
Removing empty process `U$$2.$group_0'.
Removing empty process `U$$1.$group_1'.
Removing empty process `U$$1.$group_0'.
Found and cleaned up 1 empty switch in `\wb_decoder.$group_5'.
Removing empty process `wb_decoder.$group_5'.
Found and cleaned up 1 empty switch in `\wb_decoder.$group_6'.
Removing empty process `wb_decoder.$group_6'.
Found and cleaned up 4 empty switches in `\csr_bridge_0.$group_5'.
Removing empty process `csr_bridge_0.$group_5'.
Found and cleaned up 2 empty switches in `\csr_bridge_0.$group_4'.
Removing empty process `csr_bridge_0.$group_4'.
Found and cleaned up 2 empty switches in `\csr_bridge_0.$group_3'.
Removing empty process `csr_bridge_0.$group_3'.
Found and cleaned up 2 empty switches in `\csr_bridge_0.$group_2'.
Removing empty process `csr_bridge_0.$group_2'.
Found and cleaned up 4 empty switches in `\csr_bridge_0.$group_7'.
Removing empty process `csr_bridge_0.$group_7'.
Found and cleaned up 3 empty switches in `\csr_bridge_0.$group_6'.
Removing empty process `csr_bridge_0.$group_6'.
Found and cleaned up 2 empty switches in `\csr_mux_0.$group_15'.
Removing empty process `csr_mux_0.$group_15'.
Found and cleaned up 4 empty switches in `\csr_mux_0.$group_14'.
Removing empty process `csr_mux_0.$group_14'.
Found and cleaned up 1 empty switch in `\csr_mux_0.$group_13'.
Removing empty process `csr_mux_0.$group_13'.
Found and cleaned up 2 empty switches in `\csr_mux_0.$group_12'.
Removing empty process `csr_mux_0.$group_12'.
Found and cleaned up 1 empty switch in `\csr_mux_0.$group_18'.
Removing empty process `csr_mux_0.$group_18'.
Found and cleaned up 2 empty switches in `\csr_mux_0.$group_10'.
Removing empty process `csr_mux_0.$group_10'.
Found and cleaned up 4 empty switches in `\csr_mux_0.$group_9'.
Removing empty process `csr_mux_0.$group_9'.
Found and cleaned up 1 empty switch in `\csr_mux_0.$group_8'.
Removing empty process `csr_mux_0.$group_8'.
Found and cleaned up 2 empty switches in `\csr_mux_0.$group_7'.
Removing empty process `csr_mux_0.$group_7'.
Found and cleaned up 2 empty switches in `\csr_mux_0.$group_17'.
Removing empty process `csr_mux_0.$group_17'.
Found and cleaned up 2 empty switches in `\csr_mux_0.$group_5'.
Removing empty process `csr_mux_0.$group_5'.
Found and cleaned up 4 empty switches in `\csr_mux_0.$group_4'.
Removing empty process `csr_mux_0.$group_4'.
Found and cleaned up 1 empty switch in `\csr_mux_0.$group_3'.
Removing empty process `csr_mux_0.$group_3'.
Found and cleaned up 2 empty switches in `\csr_mux_0.$group_2'.
Removing empty process `csr_mux_0.$group_2'.
Found and cleaned up 4 empty switches in `\csr_mux_0.$group_19'.
Removing empty process `csr_mux_0.$group_19'.
Found and cleaned up 2 empty switches in `\csr_mux_0.$group_0'.
Removing empty process `csr_mux_0.$group_0'.
Found and cleaned up 1 empty switch in `\decoder.$group_15'.
Removing empty process `decoder.$group_15'.
Found and cleaned up 1 empty switch in `\decoder.$group_18'.
Removing empty process `decoder.$group_18'.
Found and cleaned up 1 empty switch in `\decoder.$group_17'.
Removing empty process `decoder.$group_17'.
Found and cleaned up 1 empty switch in `\decoder.$group_16'.
Removing empty process `decoder.$group_16'.
Found and cleaned up 1 empty switch in `\sysclk.$group_1'.
Removing empty process `sysclk.$group_1'.
Removing empty process `sysclk.$group_2'.
Cleaned up 1540 empty switches.

12. Executing PMUXTREE pass.

13. Executing MEMORY_COLLECT pass (generating $mem cells).

14. Executing EXTRACT_FA pass (find and extract full/half adders).
Extracting full/half adders from top:
Extracting full/half adders from pin_ddr3_0__clk:
Extracting full/half adders from pin_rst_0:
Extracting full/half adders from pin_clk100_0:
Extracting full/half adders from pin_wishbone_0__we:
Extracting full/half adders from pin_wishbone_0__ack:
Extracting full/half adders from pin_wishbone_0__sel:
Extracting full/half adders from pin_wishbone_0__stb:
Extracting full/half adders from pin_wishbone_0__cyc:
Extracting full/half adders from pin_wishbone_0__dat_w:
Extracting full/half adders from pin_wishbone_0__dat_r:
Extracting full/half adders from pin_wishbone_0__adr:
Extracting full/half adders from pin_ddr3_0__odt:
Extracting full/half adders from pin_ddr3_0__dm:
Extracting full/half adders from pin_ddr3_0__ba:
Extracting full/half adders from pin_ddr3_0__a:
Extracting full/half adders from pin_ddr3_0__cas:
Extracting full/half adders from pin_ddr3_0__ras:
Extracting full/half adders from pin_ddr3_0__cs:
Extracting full/half adders from pin_ddr3_0__we:
Extracting full/half adders from pin_ddr3_0__clk_en:
Extracting full/half adders from pin_ddr3_0__rst:
Extracting full/half adders from drambone:
Extracting full/half adders from dramcore:
Extracting full/half adders from crossbar:
Extracting full/half adders from U$$9:
Extracting full/half adders from U$$8:
Extracting full/half adders from U$$7:
Extracting full/half adders from U$$6:
Extracting full/half adders from U$$5:
Extracting full/half adders from U$$4:
Extracting full/half adders from U$$3:
Extracting full/half adders from U$$2$66:
Extracting full/half adders from U$$1$65:
Extracting full/half adders from U$$0$64:
Extracting full/half adders from controller:
Extracting full/half adders from multiplexer:
Extracting full/half adders from write_antistarvation:
Extracting full/half adders from read_antistarvation:
Extracting full/half adders from twtrcon:
Extracting full/half adders from tccdcon:
Extracting full/half adders from tfawcon:
Extracting full/half adders from trrdcon:
Extracting full/half adders from steerer:
Extracting full/half adders from choose_req:
Extracting full/half adders from arbiter$63:
Extracting full/half adders from choose_cmd:
Extracting full/half adders from arbiter:
Extracting full/half adders from bankmachine7:
Extracting full/half adders from U$$1$62:
Extracting full/half adders from U$$0$60:
Extracting full/half adders from fifo$61:
Extracting full/half adders from trascon$59:
Extracting full/half adders from trccon$58:
Extracting full/half adders from twtpcon$57:
Extracting full/half adders from current_slicer$56:
Extracting full/half adders from lookahead_slicer$55:
Extracting full/half adders from bankmachine6:
Extracting full/half adders from U$$1$54:
Extracting full/half adders from U$$0$52:
Extracting full/half adders from fifo$53:
Extracting full/half adders from trascon$51:
Extracting full/half adders from trccon$50:
Extracting full/half adders from twtpcon$49:
Extracting full/half adders from current_slicer$48:
Extracting full/half adders from lookahead_slicer$47:
Extracting full/half adders from bankmachine5:
Extracting full/half adders from U$$1$46:
Extracting full/half adders from U$$0$44:
Extracting full/half adders from fifo$45:
Extracting full/half adders from trascon$43:
Extracting full/half adders from trccon$42:
Extracting full/half adders from twtpcon$41:
Extracting full/half adders from current_slicer$40:
Extracting full/half adders from lookahead_slicer$39:
Extracting full/half adders from bankmachine4:
Extracting full/half adders from U$$1$38:
Extracting full/half adders from U$$0$36:
Extracting full/half adders from fifo$37:
Extracting full/half adders from trascon$35:
Extracting full/half adders from trccon$34:
Extracting full/half adders from twtpcon$33:
Extracting full/half adders from current_slicer$32:
Extracting full/half adders from lookahead_slicer$31:
Extracting full/half adders from bankmachine3:
Extracting full/half adders from U$$1$30:
Extracting full/half adders from U$$0$28:
Extracting full/half adders from fifo$29:
Extracting full/half adders from trascon$27:
Extracting full/half adders from trccon$26:
Extracting full/half adders from twtpcon$25:
Extracting full/half adders from current_slicer$24:
Extracting full/half adders from lookahead_slicer$23:
Extracting full/half adders from bankmachine2:
Extracting full/half adders from U$$1$22:
Extracting full/half adders from U$$0$20:
Extracting full/half adders from fifo$21:
Extracting full/half adders from trascon$19:
Extracting full/half adders from trccon$18:
Extracting full/half adders from twtpcon$17:
Extracting full/half adders from current_slicer$16:
Extracting full/half adders from lookahead_slicer$15:
Extracting full/half adders from bankmachine1:
Extracting full/half adders from U$$1$14:
Extracting full/half adders from U$$0$12:
Extracting full/half adders from fifo$13:
Extracting full/half adders from trascon$11:
Extracting full/half adders from trccon$10:
Extracting full/half adders from twtpcon$9:
Extracting full/half adders from current_slicer$8:
Extracting full/half adders from lookahead_slicer$7:
Extracting full/half adders from bankmachine0:
Extracting full/half adders from U$$1$6:
Extracting full/half adders from U$$0:
Extracting full/half adders from fifo:
Extracting full/half adders from trascon:
Extracting full/half adders from trccon:
Extracting full/half adders from twtpcon:
Extracting full/half adders from current_slicer:
Extracting full/half adders from lookahead_slicer:
Extracting full/half adders from refresher:
Extracting full/half adders from zqcs_executer:
Extracting full/half adders from timeline$5:
Extracting full/half adders from zqcs_timer:
Extracting full/half adders from sequencer:
Extracting full/half adders from executer:
Extracting full/half adders from timeline:
Extracting full/half adders from postponer:
Extracting full/half adders from timer:
Extracting full/half adders from dfii:
Extracting full/half adders from phase_1:
Extracting full/half adders from phase_0:
Extracting full/half adders from bridge$1:
Extracting full/half adders from wb_decoder$4:
Extracting full/half adders from csr_bridge_0$3:
Extracting full/half adders from csr_mux_0$2:
Extracting full/half adders from ddrphy:
Extracting full/half adders from dqsbufm_manager1:
Extracting full/half adders from dqsbufm_manager0:
Extracting full/half adders from init:
Extracting full/half adders from U$$2:
Extracting full/half adders from U$$1:
Extracting full/half adders from bridge:
Extracting full/half adders from wb_decoder:
Extracting full/half adders from csr_bridge_0:
Extracting full/half adders from csr_mux_0:
Extracting full/half adders from decoder:
Extracting full/half adders from sysclk:
Extracting full/half adders from pll:
Removed 728 unused cells and 3632 unused wires.

15. Executing OPT pass (performing simple optimizations).

15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module U$$0.
Optimizing module U$$0$12.
Optimizing module U$$0$20.
Optimizing module U$$0$28.
Optimizing module U$$0$36.
Optimizing module U$$0$44.
Optimizing module U$$0$52.
Optimizing module U$$0$60.
Optimizing module U$$0$64.
Optimizing module U$$1.
Optimizing module U$$1$14.
Optimizing module U$$1$22.
Optimizing module U$$1$30.
Optimizing module U$$1$38.
Optimizing module U$$1$46.
Optimizing module U$$1$54.
Optimizing module U$$1$6.
Optimizing module U$$1$62.
Optimizing module U$$1$65.
Optimizing module U$$2.
<suppressed ~1 debug messages>
Optimizing module U$$2$66.
Optimizing module U$$3.
Optimizing module U$$4.
Optimizing module U$$5.
Optimizing module U$$6.
Optimizing module U$$7.
Optimizing module U$$8.
Optimizing module U$$9.
Optimizing module arbiter.
<suppressed ~3 debug messages>
Optimizing module arbiter$63.
<suppressed ~3 debug messages>
Optimizing module bankmachine0.
<suppressed ~11 debug messages>
Optimizing module bankmachine1.
<suppressed ~11 debug messages>
Optimizing module bankmachine2.
<suppressed ~11 debug messages>
Optimizing module bankmachine3.
<suppressed ~11 debug messages>
Optimizing module bankmachine4.
<suppressed ~11 debug messages>
Optimizing module bankmachine5.
<suppressed ~11 debug messages>
Optimizing module bankmachine6.
<suppressed ~11 debug messages>
Optimizing module bankmachine7.
<suppressed ~11 debug messages>
Optimizing module bridge.
Optimizing module bridge$1.
Optimizing module choose_cmd.
<suppressed ~49 debug messages>
Optimizing module choose_req.
<suppressed ~41 debug messages>
Optimizing module controller.
Optimizing module crossbar.
<suppressed ~293 debug messages>
Optimizing module csr_bridge_0.
<suppressed ~9 debug messages>
Optimizing module csr_bridge_0$3.
<suppressed ~9 debug messages>
Optimizing module csr_mux_0.
<suppressed ~43 debug messages>
Optimizing module csr_mux_0$2.
<suppressed ~18 debug messages>
Optimizing module current_slicer.
Optimizing module current_slicer$16.
Optimizing module current_slicer$24.
Optimizing module current_slicer$32.
Optimizing module current_slicer$40.
Optimizing module current_slicer$48.
Optimizing module current_slicer$56.
Optimizing module current_slicer$8.
Optimizing module ddrphy.
Optimizing module decoder.
<suppressed ~4 debug messages>
Optimizing module dfii.
Optimizing module dqsbufm_manager0.
<suppressed ~2 debug messages>
Optimizing module dqsbufm_manager1.
<suppressed ~2 debug messages>
Optimizing module drambone.
<suppressed ~21 debug messages>
Optimizing module dramcore.
Optimizing module executer.
Optimizing module fifo.
<suppressed ~1 debug messages>
Optimizing module fifo$13.
<suppressed ~1 debug messages>
Optimizing module fifo$21.
<suppressed ~1 debug messages>
Optimizing module fifo$29.
<suppressed ~1 debug messages>
Optimizing module fifo$37.
<suppressed ~1 debug messages>
Optimizing module fifo$45.
<suppressed ~1 debug messages>
Optimizing module fifo$53.
<suppressed ~1 debug messages>
Optimizing module fifo$61.
<suppressed ~1 debug messages>
Optimizing module init.
Optimizing module lookahead_slicer.
Optimizing module lookahead_slicer$15.
Optimizing module lookahead_slicer$23.
Optimizing module lookahead_slicer$31.
Optimizing module lookahead_slicer$39.
Optimizing module lookahead_slicer$47.
Optimizing module lookahead_slicer$55.
Optimizing module lookahead_slicer$7.
Optimizing module multiplexer.
<suppressed ~8 debug messages>
Optimizing module phase_0.
Optimizing module phase_1.
Optimizing module pin_clk100_0.
Optimizing module pin_ddr3_0__a.
Optimizing module pin_ddr3_0__ba.
Optimizing module pin_ddr3_0__cas.
Optimizing module pin_ddr3_0__clk.
Optimizing module pin_ddr3_0__clk_en.
Optimizing module pin_ddr3_0__cs.
Optimizing module pin_ddr3_0__dm.
Optimizing module pin_ddr3_0__odt.
Optimizing module pin_ddr3_0__ras.
Optimizing module pin_ddr3_0__rst.
Optimizing module pin_ddr3_0__we.
Optimizing module pin_rst_0.
Optimizing module pin_wishbone_0__ack.
Optimizing module pin_wishbone_0__adr.
Optimizing module pin_wishbone_0__cyc.
Optimizing module pin_wishbone_0__dat_r.
Optimizing module pin_wishbone_0__dat_w.
Optimizing module pin_wishbone_0__sel.
Optimizing module pin_wishbone_0__stb.
Optimizing module pin_wishbone_0__we.
Optimizing module pll.
Optimizing module postponer.
<suppressed ~4 debug messages>
Optimizing module read_antistarvation.
<suppressed ~4 debug messages>
Optimizing module refresher.
<suppressed ~2 debug messages>
Optimizing module sequencer.
<suppressed ~3 debug messages>
Optimizing module steerer.
<suppressed ~22 debug messages>
Optimizing module sysclk.
<suppressed ~2 debug messages>
Optimizing module tccdcon.
<suppressed ~3 debug messages>
Optimizing module tfawcon.
Optimizing module timeline.
<suppressed ~6 debug messages>
Optimizing module timeline$5.
<suppressed ~7 debug messages>
Optimizing module timer.
<suppressed ~2 debug messages>
Optimizing module top.
Optimizing module trascon.
<suppressed ~2 debug messages>
Optimizing module trascon$11.
<suppressed ~2 debug messages>
Optimizing module trascon$19.
<suppressed ~2 debug messages>
Optimizing module trascon$27.
<suppressed ~2 debug messages>
Optimizing module trascon$35.
<suppressed ~2 debug messages>
Optimizing module trascon$43.
<suppressed ~2 debug messages>
Optimizing module trascon$51.
<suppressed ~2 debug messages>
Optimizing module trascon$59.
<suppressed ~2 debug messages>
Optimizing module trccon.
<suppressed ~2 debug messages>
Optimizing module trccon$10.
<suppressed ~2 debug messages>
Optimizing module trccon$18.
<suppressed ~2 debug messages>
Optimizing module trccon$26.
<suppressed ~2 debug messages>
Optimizing module trccon$34.
<suppressed ~2 debug messages>
Optimizing module trccon$42.
<suppressed ~2 debug messages>
Optimizing module trccon$50.
<suppressed ~2 debug messages>
Optimizing module trccon$58.
<suppressed ~2 debug messages>
Optimizing module trrdcon.
<suppressed ~3 debug messages>
Optimizing module twtpcon.
<suppressed ~2 debug messages>
Optimizing module twtpcon$17.
<suppressed ~2 debug messages>
Optimizing module twtpcon$25.
<suppressed ~2 debug messages>
Optimizing module twtpcon$33.
<suppressed ~2 debug messages>
Optimizing module twtpcon$41.
<suppressed ~2 debug messages>
Optimizing module twtpcon$49.
<suppressed ~2 debug messages>
Optimizing module twtpcon$57.
<suppressed ~2 debug messages>
Optimizing module twtpcon$9.
<suppressed ~2 debug messages>
Optimizing module twtrcon.
<suppressed ~2 debug messages>
Optimizing module wb_decoder.
<suppressed ~6 debug messages>
Optimizing module wb_decoder$4.
<suppressed ~6 debug messages>
Optimizing module write_antistarvation.
<suppressed ~4 debug messages>
Optimizing module zqcs_executer.
Optimizing module zqcs_timer.
<suppressed ~2 debug messages>

15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\U$$0'.
Finding identical cells in module `\U$$0$12'.
Finding identical cells in module `\U$$0$20'.
Finding identical cells in module `\U$$0$28'.
Finding identical cells in module `\U$$0$36'.
Finding identical cells in module `\U$$0$44'.
Finding identical cells in module `\U$$0$52'.
Finding identical cells in module `\U$$0$60'.
Finding identical cells in module `\U$$0$64'.
Finding identical cells in module `\U$$1'.
Finding identical cells in module `\U$$1$14'.
<suppressed ~12 debug messages>
Finding identical cells in module `\U$$1$22'.
<suppressed ~12 debug messages>
Finding identical cells in module `\U$$1$30'.
<suppressed ~12 debug messages>
Finding identical cells in module `\U$$1$38'.
<suppressed ~12 debug messages>
Finding identical cells in module `\U$$1$46'.
<suppressed ~12 debug messages>
Finding identical cells in module `\U$$1$54'.
<suppressed ~12 debug messages>
Finding identical cells in module `\U$$1$6'.
<suppressed ~12 debug messages>
Finding identical cells in module `\U$$1$62'.
<suppressed ~12 debug messages>
Finding identical cells in module `\U$$1$65'.
Finding identical cells in module `\U$$2'.
<suppressed ~3 debug messages>
Finding identical cells in module `\U$$2$66'.
Finding identical cells in module `\U$$3'.
Finding identical cells in module `\U$$4'.
Finding identical cells in module `\U$$5'.
Finding identical cells in module `\U$$6'.
Finding identical cells in module `\U$$7'.
Finding identical cells in module `\U$$8'.
Finding identical cells in module `\U$$9'.
Finding identical cells in module `\arbiter'.
Finding identical cells in module `\arbiter$63'.
Finding identical cells in module `\bankmachine0'.
<suppressed ~114 debug messages>
Finding identical cells in module `\bankmachine1'.
<suppressed ~114 debug messages>
Finding identical cells in module `\bankmachine2'.
<suppressed ~114 debug messages>
Finding identical cells in module `\bankmachine3'.
<suppressed ~114 debug messages>
Finding identical cells in module `\bankmachine4'.
<suppressed ~114 debug messages>
Finding identical cells in module `\bankmachine5'.
<suppressed ~114 debug messages>
Finding identical cells in module `\bankmachine6'.
<suppressed ~114 debug messages>
Finding identical cells in module `\bankmachine7'.
<suppressed ~114 debug messages>
Finding identical cells in module `\bridge'.
Finding identical cells in module `\bridge$1'.
Finding identical cells in module `\choose_cmd'.
<suppressed ~243 debug messages>
Finding identical cells in module `\choose_req'.
<suppressed ~243 debug messages>
Finding identical cells in module `\controller'.
Finding identical cells in module `\crossbar'.
<suppressed ~261 debug messages>
Finding identical cells in module `\csr_bridge_0'.
<suppressed ~123 debug messages>
Finding identical cells in module `\csr_bridge_0$3'.
<suppressed ~123 debug messages>
Finding identical cells in module `\csr_mux_0'.
<suppressed ~21 debug messages>
Finding identical cells in module `\csr_mux_0$2'.
<suppressed ~6 debug messages>
Finding identical cells in module `\current_slicer'.
Finding identical cells in module `\current_slicer$16'.
Finding identical cells in module `\current_slicer$24'.
Finding identical cells in module `\current_slicer$32'.
Finding identical cells in module `\current_slicer$40'.
Finding identical cells in module `\current_slicer$48'.
Finding identical cells in module `\current_slicer$56'.
Finding identical cells in module `\current_slicer$8'.
Finding identical cells in module `\ddrphy'.
<suppressed ~291 debug messages>
Finding identical cells in module `\decoder'.
<suppressed ~9 debug messages>
Finding identical cells in module `\dfii'.
<suppressed ~3 debug messages>
Finding identical cells in module `\dqsbufm_manager0'.
<suppressed ~9 debug messages>
Finding identical cells in module `\dqsbufm_manager1'.
<suppressed ~9 debug messages>
Finding identical cells in module `\drambone'.
<suppressed ~51 debug messages>
Finding identical cells in module `\dramcore'.
Finding identical cells in module `\executer'.
Finding identical cells in module `\fifo'.
<suppressed ~15 debug messages>
Finding identical cells in module `\fifo$13'.
<suppressed ~15 debug messages>
Finding identical cells in module `\fifo$21'.
<suppressed ~15 debug messages>
Finding identical cells in module `\fifo$29'.
<suppressed ~15 debug messages>
Finding identical cells in module `\fifo$37'.
<suppressed ~15 debug messages>
Finding identical cells in module `\fifo$45'.
<suppressed ~15 debug messages>
Finding identical cells in module `\fifo$53'.
<suppressed ~15 debug messages>
Finding identical cells in module `\fifo$61'.
<suppressed ~15 debug messages>
Finding identical cells in module `\init'.
Finding identical cells in module `\lookahead_slicer'.
Finding identical cells in module `\lookahead_slicer$15'.
Finding identical cells in module `\lookahead_slicer$23'.
Finding identical cells in module `\lookahead_slicer$31'.
Finding identical cells in module `\lookahead_slicer$39'.
Finding identical cells in module `\lookahead_slicer$47'.
Finding identical cells in module `\lookahead_slicer$55'.
Finding identical cells in module `\lookahead_slicer$7'.
Finding identical cells in module `\multiplexer'.
<suppressed ~108 debug messages>
Finding identical cells in module `\phase_0'.
Finding identical cells in module `\phase_1'.
Finding identical cells in module `\pin_clk100_0'.
Finding identical cells in module `\pin_ddr3_0__a'.
Finding identical cells in module `\pin_ddr3_0__ba'.
Finding identical cells in module `\pin_ddr3_0__cas'.
Finding identical cells in module `\pin_ddr3_0__clk'.
Finding identical cells in module `\pin_ddr3_0__clk_en'.
Finding identical cells in module `\pin_ddr3_0__cs'.
Finding identical cells in module `\pin_ddr3_0__dm'.
Finding identical cells in module `\pin_ddr3_0__odt'.
Finding identical cells in module `\pin_ddr3_0__ras'.
Finding identical cells in module `\pin_ddr3_0__rst'.
Finding identical cells in module `\pin_ddr3_0__we'.
Finding identical cells in module `\pin_rst_0'.
Finding identical cells in module `\pin_wishbone_0__ack'.
Finding identical cells in module `\pin_wishbone_0__adr'.
Finding identical cells in module `\pin_wishbone_0__cyc'.
Finding identical cells in module `\pin_wishbone_0__dat_r'.
Finding identical cells in module `\pin_wishbone_0__dat_w'.
Finding identical cells in module `\pin_wishbone_0__sel'.
Finding identical cells in module `\pin_wishbone_0__stb'.
Finding identical cells in module `\pin_wishbone_0__we'.
Finding identical cells in module `\pll'.
Finding identical cells in module `\postponer'.
<suppressed ~3 debug messages>
Finding identical cells in module `\read_antistarvation'.
<suppressed ~6 debug messages>
Finding identical cells in module `\refresher'.
<suppressed ~27 debug messages>
Finding identical cells in module `\sequencer'.
Finding identical cells in module `\steerer'.
<suppressed ~264 debug messages>
Finding identical cells in module `\sysclk'.
Finding identical cells in module `\tccdcon'.
<suppressed ~3 debug messages>
Finding identical cells in module `\tfawcon'.
Finding identical cells in module `\timeline'.
<suppressed ~54 debug messages>
Finding identical cells in module `\timeline$5'.
<suppressed ~63 debug messages>
Finding identical cells in module `\timer'.
<suppressed ~6 debug messages>
Finding identical cells in module `\top'.
Finding identical cells in module `\trascon'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trascon$11'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trascon$19'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trascon$27'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trascon$35'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trascon$43'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trascon$51'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trascon$59'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trccon'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trccon$10'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trccon$18'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trccon$26'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trccon$34'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trccon$42'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trccon$50'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trccon$58'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trrdcon'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtpcon'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtpcon$17'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtpcon$25'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtpcon$33'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtpcon$41'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtpcon$49'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtpcon$57'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtpcon$9'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtrcon'.
<suppressed ~3 debug messages>
Finding identical cells in module `\wb_decoder'.
<suppressed ~3 debug messages>
Finding identical cells in module `\wb_decoder$4'.
<suppressed ~3 debug messages>
Finding identical cells in module `\write_antistarvation'.
<suppressed ~6 debug messages>
Finding identical cells in module `\zqcs_executer'.
Finding identical cells in module `\zqcs_timer'.
<suppressed ~6 debug messages>
Removed a total of 1051 cells.

15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \U$$0..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$12..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$20..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$28..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$36..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$44..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$52..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$60..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$64..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$14..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \U$$1$22..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \U$$1$30..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \U$$1$38..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \U$$1$46..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \U$$1$54..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \U$$1$6..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \U$$1$62..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \U$$1$65..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$2..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \U$$2$66..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$3..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$5..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$6..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$7..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$8..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \U$$9..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \arbiter..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \arbiter$63..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine0..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine1..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine2..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine4..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine5..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine6..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine7..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bridge..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \bridge$1..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \choose_cmd..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \choose_req..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \controller..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \crossbar..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \csr_bridge_0..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port A of cell $procmux$4948: \wb__ack -> 1'0
      Replacing known input bits on port B of cell $auto$pmuxtree.cc:65:recursive_mux_generator$6896: $auto$rtlil.cc:2443:Mux$6889 -> 1'0
      Replacing known input bits on port B of cell $auto$pmuxtree.cc:65:recursive_mux_generator$6892: \wb__ack -> 1'0
      Replacing known input bits on port B of cell $auto$pmuxtree.cc:65:recursive_mux_generator$6890: \wb__ack -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \csr_bridge_0$3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port A of cell $procmux$3761: \wb__ack -> 1'0
      Replacing known input bits on port B of cell $auto$pmuxtree.cc:65:recursive_mux_generator$6688: $auto$rtlil.cc:2443:Mux$6681 -> 1'0
      Replacing known input bits on port B of cell $auto$pmuxtree.cc:65:recursive_mux_generator$6684: \wb__ack -> 1'0
      Replacing known input bits on port B of cell $auto$pmuxtree.cc:65:recursive_mux_generator$6682: \wb__ack -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \csr_mux_0..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \csr_mux_0$2..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \current_slicer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$16..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$24..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$32..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$40..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$48..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$56..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$8..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \ddrphy..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \decoder..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \dfii..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \dqsbufm_manager0..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \dqsbufm_manager1..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \drambone..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \dramcore..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \executer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \fifo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$13..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$21..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$29..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$37..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$45..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$53..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$61..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \init..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \lookahead_slicer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$15..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$23..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$31..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$39..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$47..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$55..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$7..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \multiplexer..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \phase_0..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \phase_1..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \pin_clk100_0..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__a..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__ba..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__cas..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__clk..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__clk_en..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__cs..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__dm..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__odt..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__ras..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__rst..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__we..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_rst_0..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__ack..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__adr..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__cyc..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__dat_r..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__dat_w..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__sel..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__stb..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__we..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pll..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \postponer..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \read_antistarvation..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \refresher..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \sequencer..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port A of cell $procmux$3477: \count -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \steerer..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \sysclk..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \tccdcon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$557: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$555: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \tfawcon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \timeline..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \timeline$5..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \timer..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \trascon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$3326: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$3324: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$11..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$3054: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$3052: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$19..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$2782: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$2780: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$27..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$2510: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$2508: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$35..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$2238: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$2236: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$43..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$1966: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$1964: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$51..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$1694: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$1692: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$59..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$1422: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$1420: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$3340: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$3338: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$10..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$3068: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$3066: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$18..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$2796: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$2794: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$26..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$2524: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$2522: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$34..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$2252: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$2250: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$42..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$1980: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$1978: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$50..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$1708: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$1706: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$58..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$1436: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$1434: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \trrdcon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$580: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$578: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$3354: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$3352: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$17..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$2810: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$2808: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$25..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$2538: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$2536: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$33..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$2266: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$2264: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$41..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$1994: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$1992: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$49..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$1722: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$1720: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$57..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$1450: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$1448: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$9..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$3082: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$3080: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \twtrcon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$543: \ready -> 1'1
      Replacing known input bits on port A of cell $procmux$541: \ready -> 1'0
  Analyzing evaluation results.
Running muxtree optimizer on module \wb_decoder..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \wb_decoder$4..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \write_antistarvation..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \zqcs_executer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \zqcs_timer..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~653 debug messages>

15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \U$$0.
  Optimizing cells in module \U$$0$12.
  Optimizing cells in module \U$$0$20.
  Optimizing cells in module \U$$0$28.
  Optimizing cells in module \U$$0$36.
  Optimizing cells in module \U$$0$44.
  Optimizing cells in module \U$$0$52.
  Optimizing cells in module \U$$0$60.
  Optimizing cells in module \U$$0$64.
  Optimizing cells in module \U$$1.
  Optimizing cells in module \U$$1$14.
  Optimizing cells in module \U$$1$22.
  Optimizing cells in module \U$$1$30.
  Optimizing cells in module \U$$1$38.
  Optimizing cells in module \U$$1$46.
  Optimizing cells in module \U$$1$54.
  Optimizing cells in module \U$$1$6.
  Optimizing cells in module \U$$1$62.
  Optimizing cells in module \U$$1$65.
  Optimizing cells in module \U$$2.
  Optimizing cells in module \U$$2$66.
  Optimizing cells in module \U$$3.
  Optimizing cells in module \U$$4.
  Optimizing cells in module \U$$5.
  Optimizing cells in module \U$$6.
  Optimizing cells in module \U$$7.
  Optimizing cells in module \U$$8.
  Optimizing cells in module \U$$9.
  Optimizing cells in module \arbiter.
  Optimizing cells in module \arbiter$63.
  Optimizing cells in module \bankmachine0.
  Optimizing cells in module \bankmachine1.
  Optimizing cells in module \bankmachine2.
  Optimizing cells in module \bankmachine3.
  Optimizing cells in module \bankmachine4.
  Optimizing cells in module \bankmachine5.
  Optimizing cells in module \bankmachine6.
  Optimizing cells in module \bankmachine7.
  Optimizing cells in module \bridge.
  Optimizing cells in module \bridge$1.
  Optimizing cells in module \choose_cmd.
  Optimizing cells in module \choose_req.
  Optimizing cells in module \controller.
  Optimizing cells in module \crossbar.
  Optimizing cells in module \csr_bridge_0.
  Optimizing cells in module \csr_bridge_0$3.
  Optimizing cells in module \csr_mux_0.
  Optimizing cells in module \csr_mux_0$2.
  Optimizing cells in module \current_slicer.
  Optimizing cells in module \current_slicer$16.
  Optimizing cells in module \current_slicer$24.
  Optimizing cells in module \current_slicer$32.
  Optimizing cells in module \current_slicer$40.
  Optimizing cells in module \current_slicer$48.
  Optimizing cells in module \current_slicer$56.
  Optimizing cells in module \current_slicer$8.
  Optimizing cells in module \ddrphy.
  Optimizing cells in module \decoder.
  Optimizing cells in module \dfii.
  Optimizing cells in module \dqsbufm_manager0.
  Optimizing cells in module \dqsbufm_manager1.
  Optimizing cells in module \drambone.
  Optimizing cells in module \dramcore.
  Optimizing cells in module \executer.
  Optimizing cells in module \fifo.
  Optimizing cells in module \fifo$13.
  Optimizing cells in module \fifo$21.
  Optimizing cells in module \fifo$29.
  Optimizing cells in module \fifo$37.
  Optimizing cells in module \fifo$45.
  Optimizing cells in module \fifo$53.
  Optimizing cells in module \fifo$61.
  Optimizing cells in module \init.
  Optimizing cells in module \lookahead_slicer.
  Optimizing cells in module \lookahead_slicer$15.
  Optimizing cells in module \lookahead_slicer$23.
  Optimizing cells in module \lookahead_slicer$31.
  Optimizing cells in module \lookahead_slicer$39.
  Optimizing cells in module \lookahead_slicer$47.
  Optimizing cells in module \lookahead_slicer$55.
  Optimizing cells in module \lookahead_slicer$7.
  Optimizing cells in module \multiplexer.
    New input vector for $reduce_or cell $auto$pmuxtree.cc:37:or_generator$5208: { $auto$rtlil.cc:2377:Or$5179 $procmux$478_CMP $procmux$477_CMP $procmux$474_CMP $procmux$473_CMP $auto$rtlil.cc:2377:Or$5171 }
  Optimizing cells in module \multiplexer.
  Optimizing cells in module \phase_0.
  Optimizing cells in module \phase_1.
  Optimizing cells in module \pin_clk100_0.
  Optimizing cells in module \pin_ddr3_0__a.
  Optimizing cells in module \pin_ddr3_0__ba.
  Optimizing cells in module \pin_ddr3_0__cas.
  Optimizing cells in module \pin_ddr3_0__clk.
  Optimizing cells in module \pin_ddr3_0__clk_en.
  Optimizing cells in module \pin_ddr3_0__cs.
  Optimizing cells in module \pin_ddr3_0__dm.
  Optimizing cells in module \pin_ddr3_0__odt.
  Optimizing cells in module \pin_ddr3_0__ras.
  Optimizing cells in module \pin_ddr3_0__rst.
  Optimizing cells in module \pin_ddr3_0__we.
  Optimizing cells in module \pin_rst_0.
  Optimizing cells in module \pin_wishbone_0__ack.
  Optimizing cells in module \pin_wishbone_0__adr.
  Optimizing cells in module \pin_wishbone_0__cyc.
  Optimizing cells in module \pin_wishbone_0__dat_r.
  Optimizing cells in module \pin_wishbone_0__dat_w.
  Optimizing cells in module \pin_wishbone_0__sel.
  Optimizing cells in module \pin_wishbone_0__stb.
  Optimizing cells in module \pin_wishbone_0__we.
  Optimizing cells in module \pll.
  Optimizing cells in module \postponer.
  Optimizing cells in module \read_antistarvation.
  Optimizing cells in module \refresher.
  Optimizing cells in module \sequencer.
  Optimizing cells in module \steerer.
  Optimizing cells in module \sysclk.
  Optimizing cells in module \tccdcon.
  Optimizing cells in module \tfawcon.
  Optimizing cells in module \timeline.
  Optimizing cells in module \timeline$5.
  Optimizing cells in module \timer.
  Optimizing cells in module \top.
  Optimizing cells in module \trascon.
  Optimizing cells in module \trascon$11.
  Optimizing cells in module \trascon$19.
  Optimizing cells in module \trascon$27.
  Optimizing cells in module \trascon$35.
  Optimizing cells in module \trascon$43.
  Optimizing cells in module \trascon$51.
  Optimizing cells in module \trascon$59.
  Optimizing cells in module \trccon.
  Optimizing cells in module \trccon$10.
  Optimizing cells in module \trccon$18.
  Optimizing cells in module \trccon$26.
  Optimizing cells in module \trccon$34.
  Optimizing cells in module \trccon$42.
  Optimizing cells in module \trccon$50.
  Optimizing cells in module \trccon$58.
  Optimizing cells in module \trrdcon.
  Optimizing cells in module \twtpcon.
  Optimizing cells in module \twtpcon$17.
  Optimizing cells in module \twtpcon$25.
  Optimizing cells in module \twtpcon$33.
  Optimizing cells in module \twtpcon$41.
  Optimizing cells in module \twtpcon$49.
  Optimizing cells in module \twtpcon$57.
  Optimizing cells in module \twtpcon$9.
  Optimizing cells in module \twtrcon.
  Optimizing cells in module \wb_decoder.
  Optimizing cells in module \wb_decoder$4.
  Optimizing cells in module \write_antistarvation.
  Optimizing cells in module \zqcs_executer.
  Optimizing cells in module \zqcs_timer.
Performed a total of 1 changes.

15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\U$$0'.
Finding identical cells in module `\U$$0$12'.
Finding identical cells in module `\U$$0$20'.
Finding identical cells in module `\U$$0$28'.
Finding identical cells in module `\U$$0$36'.
Finding identical cells in module `\U$$0$44'.
Finding identical cells in module `\U$$0$52'.
Finding identical cells in module `\U$$0$60'.
Finding identical cells in module `\U$$0$64'.
Finding identical cells in module `\U$$1'.
Finding identical cells in module `\U$$1$14'.
Finding identical cells in module `\U$$1$22'.
Finding identical cells in module `\U$$1$30'.
Finding identical cells in module `\U$$1$38'.
Finding identical cells in module `\U$$1$46'.
Finding identical cells in module `\U$$1$54'.
Finding identical cells in module `\U$$1$6'.
Finding identical cells in module `\U$$1$62'.
Finding identical cells in module `\U$$1$65'.
Finding identical cells in module `\U$$2'.
Finding identical cells in module `\U$$2$66'.
Finding identical cells in module `\U$$3'.
Finding identical cells in module `\U$$4'.
Finding identical cells in module `\U$$5'.
Finding identical cells in module `\U$$6'.
Finding identical cells in module `\U$$7'.
Finding identical cells in module `\U$$8'.
Finding identical cells in module `\U$$9'.
Finding identical cells in module `\arbiter'.
Finding identical cells in module `\arbiter$63'.
Finding identical cells in module `\bankmachine0'.
<suppressed ~75 debug messages>
Finding identical cells in module `\bankmachine1'.
<suppressed ~75 debug messages>
Finding identical cells in module `\bankmachine2'.
<suppressed ~75 debug messages>
Finding identical cells in module `\bankmachine3'.
<suppressed ~75 debug messages>
Finding identical cells in module `\bankmachine4'.
<suppressed ~75 debug messages>
Finding identical cells in module `\bankmachine5'.
<suppressed ~75 debug messages>
Finding identical cells in module `\bankmachine6'.
<suppressed ~75 debug messages>
Finding identical cells in module `\bankmachine7'.
<suppressed ~75 debug messages>
Finding identical cells in module `\bridge'.
Finding identical cells in module `\bridge$1'.
Finding identical cells in module `\choose_cmd'.
Finding identical cells in module `\choose_req'.
Finding identical cells in module `\controller'.
Finding identical cells in module `\crossbar'.
Finding identical cells in module `\csr_bridge_0'.
Finding identical cells in module `\csr_bridge_0$3'.
Finding identical cells in module `\csr_mux_0'.
Finding identical cells in module `\csr_mux_0$2'.
Finding identical cells in module `\current_slicer'.
Finding identical cells in module `\current_slicer$16'.
Finding identical cells in module `\current_slicer$24'.
Finding identical cells in module `\current_slicer$32'.
Finding identical cells in module `\current_slicer$40'.
Finding identical cells in module `\current_slicer$48'.
Finding identical cells in module `\current_slicer$56'.
Finding identical cells in module `\current_slicer$8'.
Finding identical cells in module `\ddrphy'.
Finding identical cells in module `\decoder'.
Finding identical cells in module `\dfii'.
Finding identical cells in module `\dqsbufm_manager0'.
Finding identical cells in module `\dqsbufm_manager1'.
Finding identical cells in module `\drambone'.
Finding identical cells in module `\dramcore'.
Finding identical cells in module `\executer'.
Finding identical cells in module `\fifo'.
Finding identical cells in module `\fifo$13'.
Finding identical cells in module `\fifo$21'.
Finding identical cells in module `\fifo$29'.
Finding identical cells in module `\fifo$37'.
Finding identical cells in module `\fifo$45'.
Finding identical cells in module `\fifo$53'.
Finding identical cells in module `\fifo$61'.
Finding identical cells in module `\init'.
Finding identical cells in module `\lookahead_slicer'.
Finding identical cells in module `\lookahead_slicer$15'.
Finding identical cells in module `\lookahead_slicer$23'.
Finding identical cells in module `\lookahead_slicer$31'.
Finding identical cells in module `\lookahead_slicer$39'.
Finding identical cells in module `\lookahead_slicer$47'.
Finding identical cells in module `\lookahead_slicer$55'.
Finding identical cells in module `\lookahead_slicer$7'.
Finding identical cells in module `\multiplexer'.
<suppressed ~6 debug messages>
Finding identical cells in module `\phase_0'.
Finding identical cells in module `\phase_1'.
Finding identical cells in module `\pin_clk100_0'.
Finding identical cells in module `\pin_ddr3_0__a'.
Finding identical cells in module `\pin_ddr3_0__ba'.
Finding identical cells in module `\pin_ddr3_0__cas'.
Finding identical cells in module `\pin_ddr3_0__clk'.
Finding identical cells in module `\pin_ddr3_0__clk_en'.
Finding identical cells in module `\pin_ddr3_0__cs'.
Finding identical cells in module `\pin_ddr3_0__dm'.
Finding identical cells in module `\pin_ddr3_0__odt'.
Finding identical cells in module `\pin_ddr3_0__ras'.
Finding identical cells in module `\pin_ddr3_0__rst'.
Finding identical cells in module `\pin_ddr3_0__we'.
Finding identical cells in module `\pin_rst_0'.
Finding identical cells in module `\pin_wishbone_0__ack'.
Finding identical cells in module `\pin_wishbone_0__adr'.
Finding identical cells in module `\pin_wishbone_0__cyc'.
Finding identical cells in module `\pin_wishbone_0__dat_r'.
Finding identical cells in module `\pin_wishbone_0__dat_w'.
Finding identical cells in module `\pin_wishbone_0__sel'.
Finding identical cells in module `\pin_wishbone_0__stb'.
Finding identical cells in module `\pin_wishbone_0__we'.
Finding identical cells in module `\pll'.
Finding identical cells in module `\postponer'.
Finding identical cells in module `\read_antistarvation'.
Finding identical cells in module `\refresher'.
Finding identical cells in module `\sequencer'.
Finding identical cells in module `\steerer'.
<suppressed ~6 debug messages>
Finding identical cells in module `\sysclk'.
Finding identical cells in module `\tccdcon'.
Finding identical cells in module `\tfawcon'.
Finding identical cells in module `\timeline'.
Finding identical cells in module `\timeline$5'.
Finding identical cells in module `\timer'.
Finding identical cells in module `\top'.
Finding identical cells in module `\trascon'.
Finding identical cells in module `\trascon$11'.
Finding identical cells in module `\trascon$19'.
Finding identical cells in module `\trascon$27'.
Finding identical cells in module `\trascon$35'.
Finding identical cells in module `\trascon$43'.
Finding identical cells in module `\trascon$51'.
Finding identical cells in module `\trascon$59'.
Finding identical cells in module `\trccon'.
Finding identical cells in module `\trccon$10'.
Finding identical cells in module `\trccon$18'.
Finding identical cells in module `\trccon$26'.
Finding identical cells in module `\trccon$34'.
Finding identical cells in module `\trccon$42'.
Finding identical cells in module `\trccon$50'.
Finding identical cells in module `\trccon$58'.
Finding identical cells in module `\trrdcon'.
Finding identical cells in module `\twtpcon'.
Finding identical cells in module `\twtpcon$17'.
Finding identical cells in module `\twtpcon$25'.
Finding identical cells in module `\twtpcon$33'.
Finding identical cells in module `\twtpcon$41'.
Finding identical cells in module `\twtpcon$49'.
Finding identical cells in module `\twtpcon$57'.
Finding identical cells in module `\twtpcon$9'.
Finding identical cells in module `\twtrcon'.
Finding identical cells in module `\wb_decoder'.
Finding identical cells in module `\wb_decoder$4'.
Finding identical cells in module `\write_antistarvation'.
Finding identical cells in module `\zqcs_executer'.
Finding identical cells in module `\zqcs_timer'.
Removed a total of 204 cells.

15.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $procdff$154 ($dff) from module U$$1$14 (D = $procmux$3034_Y, Q = \source__valid, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7022 ($sdff) from module U$$1$14 (D = \sink__valid, Q = \source__valid).
Adding SRST signal on $procdff$151 ($dff) from module U$$1$14 (D = $procmux$3018_Y, Q = \source__payload__addr, rval = 20'00000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7024 ($sdff) from module U$$1$14 (D = \sink__payload__addr, Q = \source__payload__addr).
Adding SRST signal on $procdff$150 ($dff) from module U$$1$14 (D = $procmux$3022_Y, Q = \source__payload__we, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7026 ($sdff) from module U$$1$14 (D = \sink__payload__we, Q = \source__payload__we).
Adding SRST signal on $procdff$137 ($dff) from module U$$1$22 (D = $procmux$2762_Y, Q = \source__valid, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7028 ($sdff) from module U$$1$22 (D = \sink__valid, Q = \source__valid).
Adding SRST signal on $procdff$134 ($dff) from module U$$1$22 (D = $procmux$2746_Y, Q = \source__payload__addr, rval = 20'00000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7030 ($sdff) from module U$$1$22 (D = \sink__payload__addr, Q = \source__payload__addr).
Adding SRST signal on $procdff$133 ($dff) from module U$$1$22 (D = $procmux$2750_Y, Q = \source__payload__we, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7032 ($sdff) from module U$$1$22 (D = \sink__payload__we, Q = \source__payload__we).
Adding SRST signal on $procdff$120 ($dff) from module U$$1$30 (D = $procmux$2490_Y, Q = \source__valid, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7034 ($sdff) from module U$$1$30 (D = \sink__valid, Q = \source__valid).
Adding SRST signal on $procdff$117 ($dff) from module U$$1$30 (D = $procmux$2474_Y, Q = \source__payload__addr, rval = 20'00000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7036 ($sdff) from module U$$1$30 (D = \sink__payload__addr, Q = \source__payload__addr).
Adding SRST signal on $procdff$116 ($dff) from module U$$1$30 (D = $procmux$2478_Y, Q = \source__payload__we, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7038 ($sdff) from module U$$1$30 (D = \sink__payload__we, Q = \source__payload__we).
Adding SRST signal on $procdff$99 ($dff) from module U$$1$38 (D = $procmux$2206_Y, Q = \source__payload__we, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7040 ($sdff) from module U$$1$38 (D = \sink__payload__we, Q = \source__payload__we).
Adding SRST signal on $procdff$103 ($dff) from module U$$1$38 (D = $procmux$2218_Y, Q = \source__valid, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7042 ($sdff) from module U$$1$38 (D = \sink__valid, Q = \source__valid).
Adding SRST signal on $procdff$100 ($dff) from module U$$1$38 (D = $procmux$2202_Y, Q = \source__payload__addr, rval = 20'00000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7044 ($sdff) from module U$$1$38 (D = \sink__payload__addr, Q = \source__payload__addr).
Adding SRST signal on $procdff$86 ($dff) from module U$$1$46 (D = $procmux$1946_Y, Q = \source__valid, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7046 ($sdff) from module U$$1$46 (D = \sink__valid, Q = \source__valid).
Adding SRST signal on $procdff$83 ($dff) from module U$$1$46 (D = $procmux$1930_Y, Q = \source__payload__addr, rval = 20'00000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7048 ($sdff) from module U$$1$46 (D = \sink__payload__addr, Q = \source__payload__addr).
Adding SRST signal on $procdff$82 ($dff) from module U$$1$46 (D = $procmux$1934_Y, Q = \source__payload__we, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7050 ($sdff) from module U$$1$46 (D = \sink__payload__we, Q = \source__payload__we).
Adding SRST signal on $procdff$69 ($dff) from module U$$1$54 (D = $procmux$1674_Y, Q = \source__valid, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7052 ($sdff) from module U$$1$54 (D = \sink__valid, Q = \source__valid).
Adding SRST signal on $procdff$66 ($dff) from module U$$1$54 (D = $procmux$1658_Y, Q = \source__payload__addr, rval = 20'00000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7054 ($sdff) from module U$$1$54 (D = \sink__payload__addr, Q = \source__payload__addr).
Adding SRST signal on $procdff$65 ($dff) from module U$$1$54 (D = $procmux$1662_Y, Q = \source__payload__we, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7056 ($sdff) from module U$$1$54 (D = \sink__payload__we, Q = \source__payload__we).
Adding SRST signal on $procdff$171 ($dff) from module U$$1$6 (D = $procmux$3306_Y, Q = \source__valid, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7058 ($sdff) from module U$$1$6 (D = \sink__valid, Q = \source__valid).
Adding SRST signal on $procdff$168 ($dff) from module U$$1$6 (D = $procmux$3290_Y, Q = \source__payload__addr, rval = 20'00000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7060 ($sdff) from module U$$1$6 (D = \sink__payload__addr, Q = \source__payload__addr).
Adding SRST signal on $procdff$167 ($dff) from module U$$1$6 (D = $procmux$3294_Y, Q = \source__payload__we, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7062 ($sdff) from module U$$1$6 (D = \sink__payload__we, Q = \source__payload__we).
Adding SRST signal on $procdff$52 ($dff) from module U$$1$62 (D = $procmux$1402_Y, Q = \source__valid, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7064 ($sdff) from module U$$1$62 (D = \sink__valid, Q = \source__valid).
Adding SRST signal on $procdff$49 ($dff) from module U$$1$62 (D = $procmux$1386_Y, Q = \source__payload__addr, rval = 20'00000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7066 ($sdff) from module U$$1$62 (D = \sink__payload__addr, Q = \source__payload__addr).
Adding SRST signal on $procdff$48 ($dff) from module U$$1$62 (D = $procmux$1390_Y, Q = \source__payload__we, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7068 ($sdff) from module U$$1$62 (D = \sink__payload__we, Q = \source__payload__we).
Adding SRST signal on $procdff$294 ($dff) from module U$$2 (D = $procmux$4899_Y, Q = \counter, rval = 7'0000000).
Adding EN signal on $auto$ff.cc:262:slice$7070 ($sdff) from module U$$2 (D = $procmux$4899_Y, Q = \counter).
Adding SRST signal on $procdff$293 ($dff) from module U$$2 (D = $procmux$4891_Y, Q = \freeze, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7076 ($sdff) from module U$$2 (D = 1'1, Q = \freeze).
Adding SRST signal on $procdff$290 ($dff) from module U$$2 (D = $procmux$4873_Y, Q = \pause, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7080 ($sdff) from module U$$2 (D = 1'1, Q = \pause).
Adding SRST signal on $procdff$289 ($dff) from module U$$2 (D = $procmux$4867_Y, Q = \update, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7084 ($sdff) from module U$$2 (D = 1'1, Q = \update).
Adding SRST signal on $procdff$3 ($dff) from module U$$8 (D = { \buffer [2:0] \i }, Q = \buffer, rval = 4'0000).
Adding SRST signal on $procdff$2 ($dff) from module U$$9 (D = { \buffer [12:0] \i }, Q = \buffer, rval = 14'00000000000000).
Adding SRST signal on $procdff$44 ($dff) from module arbiter (D = $procmux$1186_Y, Q = \grant, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7090 ($sdff) from module arbiter (D = $auto$rtlil.cc:2443:Mux$5891, Q = \grant).
Adding SRST signal on $procdff$42 ($dff) from module arbiter$63 (D = $procmux$945_Y, Q = \grant, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7112 ($sdff) from module arbiter$63 (D = $auto$rtlil.cc:2443:Mux$5649, Q = \grant).
Adding SRST signal on $procdff$166 ($dff) from module bankmachine0 (D = $auto$rtlil.cc:2443:Mux$6575, Q = \fsm_state, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7134 ($sdff) from module bankmachine0 (D = $auto$rtlil.cc:2443:Mux$6575, Q = \fsm_state).
Adding SRST signal on $procdff$165 ($dff) from module bankmachine0 (D = $procmux$3110_Y, Q = \row_opened, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7160 ($sdff) from module bankmachine0 (D = 1'1, Q = \row_opened).
Adding SRST signal on $procdff$164 ($dff) from module bankmachine0 (D = $procmux$3106_Y, Q = \row, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7164 ($sdff) from module bankmachine0 (D = \current_slicer_row, Q = \row).
Adding SRST signal on $procdff$149 ($dff) from module bankmachine1 (D = $auto$rtlil.cc:2443:Mux$6483, Q = \fsm_state, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7170 ($sdff) from module bankmachine1 (D = $auto$rtlil.cc:2443:Mux$6483, Q = \fsm_state).
Adding SRST signal on $procdff$148 ($dff) from module bankmachine1 (D = $procmux$2838_Y, Q = \row_opened, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7196 ($sdff) from module bankmachine1 (D = 1'1, Q = \row_opened).
Adding SRST signal on $procdff$147 ($dff) from module bankmachine1 (D = $procmux$2834_Y, Q = \row, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7200 ($sdff) from module bankmachine1 (D = \current_slicer_row, Q = \row).
Adding SRST signal on $procdff$132 ($dff) from module bankmachine2 (D = $auto$rtlil.cc:2443:Mux$6391, Q = \fsm_state, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7206 ($sdff) from module bankmachine2 (D = $auto$rtlil.cc:2443:Mux$6391, Q = \fsm_state).
Adding SRST signal on $procdff$131 ($dff) from module bankmachine2 (D = $procmux$2566_Y, Q = \row_opened, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7232 ($sdff) from module bankmachine2 (D = 1'1, Q = \row_opened).
Adding SRST signal on $procdff$130 ($dff) from module bankmachine2 (D = $procmux$2562_Y, Q = \row, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7236 ($sdff) from module bankmachine2 (D = \current_slicer_row, Q = \row).
Adding SRST signal on $procdff$115 ($dff) from module bankmachine3 (D = $auto$rtlil.cc:2443:Mux$6299, Q = \fsm_state, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7242 ($sdff) from module bankmachine3 (D = $auto$rtlil.cc:2443:Mux$6299, Q = \fsm_state).
Adding SRST signal on $procdff$114 ($dff) from module bankmachine3 (D = $procmux$2294_Y, Q = \row_opened, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7268 ($sdff) from module bankmachine3 (D = 1'1, Q = \row_opened).
Adding SRST signal on $procdff$113 ($dff) from module bankmachine3 (D = $procmux$2290_Y, Q = \row, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7272 ($sdff) from module bankmachine3 (D = \current_slicer_row, Q = \row).
Adding SRST signal on $procdff$98 ($dff) from module bankmachine4 (D = $auto$rtlil.cc:2443:Mux$6207, Q = \fsm_state, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7278 ($sdff) from module bankmachine4 (D = $auto$rtlil.cc:2443:Mux$6207, Q = \fsm_state).
Adding SRST signal on $procdff$97 ($dff) from module bankmachine4 (D = $procmux$2022_Y, Q = \row_opened, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7304 ($sdff) from module bankmachine4 (D = 1'1, Q = \row_opened).
Adding SRST signal on $procdff$96 ($dff) from module bankmachine4 (D = $procmux$2018_Y, Q = \row, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7308 ($sdff) from module bankmachine4 (D = \current_slicer_row, Q = \row).
Adding SRST signal on $procdff$81 ($dff) from module bankmachine5 (D = $auto$rtlil.cc:2443:Mux$6115, Q = \fsm_state, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7314 ($sdff) from module bankmachine5 (D = $auto$rtlil.cc:2443:Mux$6115, Q = \fsm_state).
Adding SRST signal on $procdff$80 ($dff) from module bankmachine5 (D = $procmux$1750_Y, Q = \row_opened, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7340 ($sdff) from module bankmachine5 (D = 1'1, Q = \row_opened).
Adding SRST signal on $procdff$79 ($dff) from module bankmachine5 (D = $procmux$1746_Y, Q = \row, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7344 ($sdff) from module bankmachine5 (D = \current_slicer_row, Q = \row).
Adding SRST signal on $procdff$64 ($dff) from module bankmachine6 (D = $auto$rtlil.cc:2443:Mux$6023, Q = \fsm_state, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7350 ($sdff) from module bankmachine6 (D = $auto$rtlil.cc:2443:Mux$6023, Q = \fsm_state).
Adding SRST signal on $procdff$63 ($dff) from module bankmachine6 (D = $procmux$1478_Y, Q = \row_opened, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7376 ($sdff) from module bankmachine6 (D = 1'1, Q = \row_opened).
Adding SRST signal on $procdff$62 ($dff) from module bankmachine6 (D = $procmux$1474_Y, Q = \row, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7380 ($sdff) from module bankmachine6 (D = \current_slicer_row, Q = \row).
Adding SRST signal on $procdff$47 ($dff) from module bankmachine7 (D = $auto$rtlil.cc:2443:Mux$5931, Q = \fsm_state, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7386 ($sdff) from module bankmachine7 (D = $auto$rtlil.cc:2443:Mux$5931, Q = \fsm_state).
Adding SRST signal on $procdff$46 ($dff) from module bankmachine7 (D = $procmux$1206_Y, Q = \row_opened, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7412 ($sdff) from module bankmachine7 (D = 1'1, Q = \row_opened).
Adding SRST signal on $procdff$45 ($dff) from module bankmachine7 (D = $procmux$1202_Y, Q = \row, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7416 ($sdff) from module bankmachine7 (D = \current_slicer_row, Q = \row).
Adding SRST signal on $procdff$299 ($dff) from module csr_bridge_0 (D = { $procmux$4960_Y $procmux$4984_Y $procmux$4968_Y $procmux$4977_Y }, Q = \wb__dat_r, rval = 0).
Adding EN signal on $auto$ff.cc:262:slice$7422 ($sdff) from module csr_bridge_0 (D = \csr__r_data, Q = \wb__dat_r [23:16]).
Adding EN signal on $auto$ff.cc:262:slice$7422 ($sdff) from module csr_bridge_0 (D = \csr__r_data, Q = \wb__dat_r [15:8]).
Adding EN signal on $auto$ff.cc:262:slice$7422 ($sdff) from module csr_bridge_0 (D = \csr__r_data, Q = \wb__dat_r [31:24]).
Adding EN signal on $auto$ff.cc:262:slice$7422 ($sdff) from module csr_bridge_0 (D = \csr__r_data, Q = \wb__dat_r [7:0]).
Adding SRST signal on $procdff$298 ($dff) from module csr_bridge_0 (D = $auto$rtlil.cc:2443:Mux$6891, Q = \wb__ack, rval = 1'0).
Adding SRST signal on $procdff$297 ($dff) from module csr_bridge_0 (D = $procmux$4915_Y, Q = \cycle, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7446 ($sdff) from module csr_bridge_0 (D = $auto$rtlil.cc:2443:Mux$6953, Q = \cycle).
Adding SRST signal on $procdff$209 ($dff) from module csr_bridge_0$3 (D = { $procmux$3773_Y $procmux$3797_Y $procmux$3781_Y $procmux$3790_Y }, Q = \wb__dat_r, rval = 0).
Adding EN signal on $auto$ff.cc:262:slice$7454 ($sdff) from module csr_bridge_0$3 (D = \csr__r_data, Q = \wb__dat_r [23:16]).
Adding EN signal on $auto$ff.cc:262:slice$7454 ($sdff) from module csr_bridge_0$3 (D = \csr__r_data, Q = \wb__dat_r [15:8]).
Adding EN signal on $auto$ff.cc:262:slice$7454 ($sdff) from module csr_bridge_0$3 (D = \csr__r_data, Q = \wb__dat_r [31:24]).
Adding EN signal on $auto$ff.cc:262:slice$7454 ($sdff) from module csr_bridge_0$3 (D = \csr__r_data, Q = \wb__dat_r [7:0]).
Adding SRST signal on $procdff$208 ($dff) from module csr_bridge_0$3 (D = $auto$rtlil.cc:2443:Mux$6683, Q = \wb__ack, rval = 1'0).
Adding SRST signal on $procdff$207 ($dff) from module csr_bridge_0$3 (D = $procmux$3728_Y, Q = \cycle, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7478 ($sdff) from module csr_bridge_0$3 (D = $auto$rtlil.cc:2443:Mux$6745, Q = \cycle).
Adding SRST signal on $procdff$311 ($dff) from module csr_mux_0 (D = $auto$rtlil.cc:2443:Mux$6967, Q = \burstdet__shadow_en, rval = 4'0000).
Adding SRST signal on $procdff$310 ($dff) from module csr_mux_0 (D = $procmux$5061_Y, Q = \bitslip__shadow, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7487 ($sdff) from module csr_mux_0 (D = $procmux$5059_Y, Q = \bitslip__shadow).
Adding SRST signal on $procdff$309 ($dff) from module csr_mux_0 (D = \csr__w_stb, Q = \burstdet__w_stb, rval = 1'0).
Adding SRST signal on $procdff$308 ($dff) from module csr_mux_0 (D = $procmux$5047_Y, Q = \burstdet__shadow, rval = 2'00).
Adding EN signal on $auto$ff.cc:262:slice$7498 ($sdff) from module csr_mux_0 (D = $procmux$5045_Y, Q = \burstdet__shadow).
Adding SRST signal on $procdff$307 ($dff) from module csr_mux_0 (D = $auto$rtlil.cc:2443:Mux$6981, Q = \rdly_p0__shadow_en, rval = 4'0000).
Adding SRST signal on $procdff$305 ($dff) from module csr_mux_0 (D = \csr__w_stb, Q = \rdly_p0__w_stb, rval = 1'0).
Adding SRST signal on $procdff$304 ($dff) from module csr_mux_0 (D = $procmux$5022_Y, Q = \rdly_p0__shadow, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7510 ($sdff) from module csr_mux_0 (D = $procmux$5020_Y, Q = \rdly_p0__shadow).
Adding SRST signal on $procdff$303 ($dff) from module csr_mux_0 (D = $auto$rtlil.cc:2443:Mux$6995, Q = \rdly_p1__shadow_en, rval = 4'0000).
Adding SRST signal on $procdff$302 ($dff) from module csr_mux_0 (D = \csr__w_stb, Q = \rdly_p1__w_stb, rval = 1'0).
Adding SRST signal on $procdff$301 ($dff) from module csr_mux_0 (D = $procmux$4999_Y, Q = \rdly_p1__shadow, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7522 ($sdff) from module csr_mux_0 (D = $procmux$4997_Y, Q = \rdly_p1__shadow).
Adding SRST signal on $procdff$300 ($dff) from module csr_mux_0 (D = $auto$rtlil.cc:2443:Mux$7009, Q = \bitslip__shadow_en, rval = 4'0000).
Adding SRST signal on $procdff$233 ($dff) from module csr_mux_0$2 (D = $procmux$4091_Y, Q = \dfii_control__shadow, rval = 4'0000).
Adding EN signal on $auto$ff.cc:262:slice$7529 ($sdff) from module csr_mux_0$2 (D = \csr__w_data [3:0], Q = \dfii_control__shadow).
Adding SRST signal on $procdff$232 ($dff) from module csr_mux_0$2 (D = { $procmux$4078_Y $procmux$4085_Y }, Q = \dfii_p1_address__shadow, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7533 ($sdff) from module csr_mux_0$2 (D = \csr__w_data [4:0], Q = \dfii_p1_address__shadow [12:8]).
Adding EN signal on $auto$ff.cc:262:slice$7533 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p1_address__shadow [7:0]).
Adding SRST signal on $procdff$230 ($dff) from module csr_mux_0$2 (D = $procmux$4068_Y, Q = \dfii_p0_command__shadow, rval = 6'000000).
Adding EN signal on $auto$ff.cc:262:slice$7540 ($sdff) from module csr_mux_0$2 (D = \csr__w_data [5:0], Q = \dfii_p0_command__shadow).
Adding SRST signal on $procdff$229 ($dff) from module csr_mux_0$2 (D = \csr__w_stb, Q = \dfii_p0_command_issue__w_stb, rval = 1'0).
Adding SRST signal on $procdff$225 ($dff) from module csr_mux_0$2 (D = { $procmux$4035_Y $procmux$4042_Y }, Q = \dfii_p0_address__shadow, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7549 ($sdff) from module csr_mux_0$2 (D = \csr__w_data [4:0], Q = \dfii_p0_address__shadow [12:8]).
Adding EN signal on $auto$ff.cc:262:slice$7549 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p0_address__shadow [7:0]).
Adding SRST signal on $procdff$224 ($dff) from module csr_mux_0$2 (D = $procmux$4029_Y, Q = \dfii_p1_baddress__shadow, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7556 ($sdff) from module csr_mux_0$2 (D = \csr__w_data [2:0], Q = \dfii_p1_baddress__shadow).
Adding SRST signal on $procdff$222 ($dff) from module csr_mux_0$2 (D = $procmux$4019_Y, Q = \dfii_p0_baddress__shadow, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7560 ($sdff) from module csr_mux_0$2 (D = \csr__w_data [2:0], Q = \dfii_p0_baddress__shadow).
Adding SRST signal on $procdff$221 ($dff) from module csr_mux_0$2 (D = $procmux$4013_Y, Q = \dfii_p1_rddata__shadow, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7564 ($sdff) from module csr_mux_0$2 (D = \dfii_p1_rddata__r_data, Q = \dfii_p1_rddata__shadow).
Adding SRST signal on $procdff$219 ($dff) from module csr_mux_0$2 (D = { $procmux$3933_Y $procmux$4003_Y $procmux$3941_Y $procmux$3950_Y $procmux$3960_Y $procmux$3971_Y $procmux$3983_Y $procmux$3996_Y }, Q = \dfii_p0_wrdata__shadow, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7568 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p0_wrdata__shadow [63:56]).
Adding EN signal on $auto$ff.cc:262:slice$7568 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p0_wrdata__shadow [47:40]).
Adding EN signal on $auto$ff.cc:262:slice$7568 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p0_wrdata__shadow [39:32]).
Adding EN signal on $auto$ff.cc:262:slice$7568 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p0_wrdata__shadow [31:24]).
Adding EN signal on $auto$ff.cc:262:slice$7568 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p0_wrdata__shadow [23:16]).
Adding EN signal on $auto$ff.cc:262:slice$7568 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p0_wrdata__shadow [15:8]).
Adding EN signal on $auto$ff.cc:262:slice$7568 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p0_wrdata__shadow [7:0]).
Adding EN signal on $auto$ff.cc:262:slice$7568 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p0_wrdata__shadow [55:48]).
Adding SRST signal on $procdff$218 ($dff) from module csr_mux_0$2 (D = $auto$rtlil.cc:2443:Mux$6771, Q = \dfii_p0_rddata__shadow_en, rval = 8'00000000).
Adding SRST signal on $procdff$217 ($dff) from module csr_mux_0$2 (D = $procmux$3914_Y, Q = \dfii_p0_rddata__shadow, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7594 ($sdff) from module csr_mux_0$2 (D = \dfii_p0_rddata__r_data, Q = \dfii_p0_rddata__shadow).
Adding SRST signal on $procdff$214 ($dff) from module csr_mux_0$2 (D = $procmux$3900_Y, Q = \dfii_p1_command__shadow, rval = 6'000000).
Adding EN signal on $auto$ff.cc:262:slice$7598 ($sdff) from module csr_mux_0$2 (D = \csr__w_data [5:0], Q = \dfii_p1_command__shadow).
Adding SRST signal on $procdff$213 ($dff) from module csr_mux_0$2 (D = { $procmux$3824_Y $procmux$3894_Y $procmux$3832_Y $procmux$3841_Y $procmux$3851_Y $procmux$3862_Y $procmux$3874_Y $procmux$3887_Y }, Q = \dfii_p1_wrdata__shadow, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7602 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p1_wrdata__shadow [63:56]).
Adding EN signal on $auto$ff.cc:262:slice$7602 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p1_wrdata__shadow [47:40]).
Adding EN signal on $auto$ff.cc:262:slice$7602 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p1_wrdata__shadow [39:32]).
Adding EN signal on $auto$ff.cc:262:slice$7602 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p1_wrdata__shadow [31:24]).
Adding EN signal on $auto$ff.cc:262:slice$7602 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p1_wrdata__shadow [23:16]).
Adding EN signal on $auto$ff.cc:262:slice$7602 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p1_wrdata__shadow [15:8]).
Adding EN signal on $auto$ff.cc:262:slice$7602 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p1_wrdata__shadow [7:0]).
Adding EN signal on $auto$ff.cc:262:slice$7602 ($sdff) from module csr_mux_0$2 (D = \csr__w_data, Q = \dfii_p1_wrdata__shadow [55:48]).
Adding SRST signal on $procdff$212 ($dff) from module csr_mux_0$2 (D = \csr__w_stb, Q = \dfii_p1_command_issue__w_stb, rval = 1'0).
Adding SRST signal on $procdff$210 ($dff) from module csr_mux_0$2 (D = $auto$rtlil.cc:2443:Mux$6797, Q = \dfii_p1_rddata__shadow_en, rval = 8'00000000).
Adding SRST signal on $procdff$280 ($dff) from module ddrphy (D = $procmux$4811_Y, Q = \burstdet_reg [0], rval = 1'1).
Adding SRST signal on $procdff$280 ($dff) from module ddrphy (D = $procmux$4807_Y, Q = \burstdet_reg [1], rval = 1'1).
Adding EN signal on $auto$ff.cc:262:slice$7634 ($sdff) from module ddrphy (D = 1'0, Q = \burstdet_reg [1]).
Adding EN signal on $auto$ff.cc:262:slice$7633 ($sdff) from module ddrphy (D = 1'0, Q = \burstdet_reg [0]).
Adding SRST signal on $procdff$275 ($dff) from module ddrphy (D = $382, Q = \rddata_valid, rval = 1'0).
Adding SRST signal on $procdff$269 ($dff) from module ddrphy (D = \datavalid$105, Q = \datavalid_prev$250, rval = 1'0).
Adding SRST signal on $procdff$254 ($dff) from module ddrphy (D = \datavalid, Q = \datavalid_prev, rval = 1'0).
Adding SRST signal on $procdff$250 ($dff) from module ddrphy (D = { \rddata_en_last [11:0] \ecp5phy__rddata_en }, Q = \rddata_en_last, rval = 13'0000000000000).
Adding SRST signal on $procdff$247 ($dff) from module ddrphy (D = { $procmux$4501_Y $procmux$4753_Y $procmux$4505_Y $procmux$4521_Y $procmux$4537_Y $procmux$4553_Y $procmux$4569_Y $procmux$4585_Y $procmux$4601_Y $procmux$4617_Y $procmux$4633_Y $procmux$4649_Y $procmux$4665_Y $procmux$4681_Y $procmux$4697_Y $procmux$4713_Y $procmux$4729_Y $procmux$4741_Y $procmux$4509_Y $procmux$4525_Y $procmux$4541_Y $procmux$4557_Y $procmux$4573_Y $procmux$4589_Y $procmux$4605_Y $procmux$4621_Y $procmux$4637_Y $procmux$4653_Y $procmux$4669_Y $procmux$4685_Y $procmux$4701_Y $procmux$4717_Y $procmux$4737_Y $procmux$4749_Y $procmux$4513_Y $procmux$4529_Y $procmux$4545_Y $procmux$4561_Y $procmux$4577_Y $procmux$4593_Y $procmux$4609_Y $procmux$4625_Y $procmux$4641_Y $procmux$4657_Y $procmux$4673_Y $procmux$4689_Y $procmux$4705_Y $procmux$4721_Y $procmux$4745_Y $procmux$4733_Y $procmux$4517_Y $procmux$4533_Y $procmux$4549_Y $procmux$4565_Y $procmux$4581_Y $procmux$4597_Y $procmux$4613_Y $procmux$4629_Y $procmux$4645_Y $procmux$4661_Y $procmux$4677_Y $procmux$4693_Y $procmux$4709_Y $procmux$4725_Y }, Q = \ecp5phy__rddata, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7641 ($sdff) from module ddrphy (D = { \dq_i_data$92 [3] \dq_i_data$82 [3] \dq_i_data$72 [3] \dq_i_data$62 [3] \dq_i_data$52 [3] \dq_i_data$42 [3] \dq_i_data$32 [3] \dq_i_data [3] \dq_i_data$92 [2] \dq_i_data$82 [2] \dq_i_data$72 [2] \dq_i_data$62 [2] \dq_i_data$52 [2] \dq_i_data$42 [2] \dq_i_data$32 [2] \dq_i_data [2] \dq_i_data$92 [1] \dq_i_data$82 [1] \dq_i_data$72 [1] \dq_i_data$62 [1] \dq_i_data$52 [1] \dq_i_data$42 [1] \dq_i_data$32 [1] \dq_i_data [1] \dq_i_data$92 [0] \dq_i_data$82 [0] \dq_i_data$72 [0] \dq_i_data$62 [0] \dq_i_data$52 [0] \dq_i_data$42 [0] \dq_i_data$32 [0] \dq_i_data [0] }, Q = { \ecp5phy__rddata [55:48] \ecp5phy__rddata [39:32] \ecp5phy__rddata [23:16] \ecp5phy__rddata [7:0] }).
Adding EN signal on $auto$ff.cc:262:slice$7641 ($sdff) from module ddrphy (D = { \dq_i_data$193 [3] \dq_i_data$183 [3] \dq_i_data$173 [3] \dq_i_data$163 [3] \dq_i_data$153 [3] \dq_i_data$143 [3] \dq_i_data$133 [3] \dq_i_data$123 [3] \dq_i_data$193 [2] \dq_i_data$183 [2] \dq_i_data$173 [2] \dq_i_data$163 [2] \dq_i_data$153 [2] \dq_i_data$143 [2] \dq_i_data$133 [2] \dq_i_data$123 [2] \dq_i_data$193 [1] \dq_i_data$183 [1] \dq_i_data$173 [1] \dq_i_data$163 [1] \dq_i_data$153 [1] \dq_i_data$143 [1] \dq_i_data$133 [1] \dq_i_data$123 [1] \dq_i_data$193 [0] \dq_i_data$183 [0] \dq_i_data$173 [0] \dq_i_data$163 [0] \dq_i_data$153 [0] \dq_i_data$143 [0] \dq_i_data$133 [0] \dq_i_data$123 [0] }, Q = { \ecp5phy__rddata [63:56] \ecp5phy__rddata [47:40] \ecp5phy__rddata [31:24] \ecp5phy__rddata [15:8] }).
Adding SRST signal on $procdff$246 ($dff) from module ddrphy (D = { $procmux$4119_Y $procmux$4497_Y $procmux$4125_Y $procmux$4149_Y $procmux$4173_Y $procmux$4197_Y $procmux$4221_Y $procmux$4245_Y $procmux$4269_Y $procmux$4293_Y $procmux$4317_Y $procmux$4341_Y $procmux$4365_Y $procmux$4389_Y $procmux$4413_Y $procmux$4437_Y $procmux$4461_Y $procmux$4479_Y $procmux$4131_Y $procmux$4155_Y $procmux$4179_Y $procmux$4203_Y $procmux$4227_Y $procmux$4251_Y $procmux$4275_Y $procmux$4299_Y $procmux$4323_Y $procmux$4347_Y $procmux$4371_Y $procmux$4395_Y $procmux$4419_Y $procmux$4443_Y $procmux$4473_Y $procmux$4491_Y $procmux$4137_Y $procmux$4161_Y $procmux$4185_Y $procmux$4209_Y $procmux$4233_Y $procmux$4257_Y $procmux$4281_Y $procmux$4305_Y $procmux$4329_Y $procmux$4353_Y $procmux$4377_Y $procmux$4401_Y $procmux$4425_Y $procmux$4449_Y $procmux$4485_Y $procmux$4467_Y $procmux$4143_Y $procmux$4167_Y $procmux$4191_Y $procmux$4215_Y $procmux$4239_Y $procmux$4263_Y $procmux$4287_Y $procmux$4311_Y $procmux$4335_Y $procmux$4359_Y $procmux$4383_Y $procmux$4407_Y $procmux$4431_Y $procmux$4455_Y }, Q = \ecp5phy__rddata$12, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7644 ($sdff) from module ddrphy (D = { \dq_i_data$92 [3] \dq_i_data$82 [3] \dq_i_data$72 [3] \dq_i_data$62 [3] \dq_i_data$52 [3] \dq_i_data$42 [3] \dq_i_data$32 [3] \dq_i_data [3] \dq_i_data$92 [2] \dq_i_data$82 [2] \dq_i_data$72 [2] \dq_i_data$62 [2] \dq_i_data$52 [2] \dq_i_data$42 [2] \dq_i_data$32 [2] \dq_i_data [2] \dq_i_data$92 [1] \dq_i_data$82 [1] \dq_i_data$72 [1] \dq_i_data$62 [1] \dq_i_data$52 [1] \dq_i_data$42 [1] \dq_i_data$32 [1] \dq_i_data [1] \dq_i_data$92 [0] \dq_i_data$82 [0] \dq_i_data$72 [0] \dq_i_data$62 [0] \dq_i_data$52 [0] \dq_i_data$42 [0] \dq_i_data$32 [0] \dq_i_data [0] }, Q = { \ecp5phy__rddata$12 [55:48] \ecp5phy__rddata$12 [39:32] \ecp5phy__rddata$12 [23:16] \ecp5phy__rddata$12 [7:0] }).
Adding EN signal on $auto$ff.cc:262:slice$7644 ($sdff) from module ddrphy (D = { \dq_i_data$193 [3] \dq_i_data$183 [3] \dq_i_data$173 [3] \dq_i_data$163 [3] \dq_i_data$153 [3] \dq_i_data$143 [3] \dq_i_data$133 [3] \dq_i_data$123 [3] \dq_i_data$193 [2] \dq_i_data$183 [2] \dq_i_data$173 [2] \dq_i_data$163 [2] \dq_i_data$153 [2] \dq_i_data$143 [2] \dq_i_data$133 [2] \dq_i_data$123 [2] \dq_i_data$193 [1] \dq_i_data$183 [1] \dq_i_data$173 [1] \dq_i_data$163 [1] \dq_i_data$153 [1] \dq_i_data$143 [1] \dq_i_data$133 [1] \dq_i_data$123 [1] \dq_i_data$193 [0] \dq_i_data$183 [0] \dq_i_data$173 [0] \dq_i_data$163 [0] \dq_i_data$153 [0] \dq_i_data$143 [0] \dq_i_data$133 [0] \dq_i_data$123 [0] }, Q = { \ecp5phy__rddata$12 [63:56] \ecp5phy__rddata$12 [47:40] \ecp5phy__rddata$12 [31:24] \ecp5phy__rddata$12 [15:8] }).
Adding SRST signal on $procdff$239 ($dff) from module ddrphy (D = { \wrdata_en_last [5:0] \ecp5phy__wrdata_en }, Q = \wrdata_en_last, rval = 7'0000000).
Adding SRST signal on $procdff$287 ($dff) from module dqsbufm_manager0 (D = $auto$rtlil.cc:2443:Mux$6839, Q = \pause, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7656 ($sdff) from module dqsbufm_manager0 (D = 1'1, Q = \pause).
Adding SRST signal on $procdff$286 ($dff) from module dqsbufm_manager0 (D = $auto$rtlil.cc:2443:Mux$6869, Q = \fsm_state, rval = 4'0000).
Adding EN signal on $auto$ff.cc:262:slice$7662 ($sdff) from module dqsbufm_manager0 (D = $auto$rtlil.cc:2443:Mux$6869, Q = \fsm_state).
Adding SRST signal on $procdff$285 ($dff) from module dqsbufm_manager0 (D = $procmux$4840_Y, Q = \readclksel, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7670 ($sdff) from module dqsbufm_manager0 (D = \rdly_p0__w_data, Q = \readclksel).
Adding SRST signal on $procdff$284 ($dff) from module dqsbufm_manager1 (D = $auto$rtlil.cc:2443:Mux$6803, Q = \pause, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7672 ($sdff) from module dqsbufm_manager1 (D = 1'1, Q = \pause).
Adding SRST signal on $procdff$283 ($dff) from module dqsbufm_manager1 (D = $auto$rtlil.cc:2443:Mux$6833, Q = \fsm_state, rval = 4'0000).
Adding EN signal on $auto$ff.cc:262:slice$7678 ($sdff) from module dqsbufm_manager1 (D = $auto$rtlil.cc:2443:Mux$6833, Q = \fsm_state).
Adding SRST signal on $procdff$282 ($dff) from module dqsbufm_manager1 (D = $procmux$4815_Y, Q = \readclksel, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7686 ($sdff) from module dqsbufm_manager1 (D = \rdly_p1__w_data, Q = \readclksel).
Adding SRST signal on $procdff$1 ($dff) from module drambone (D = $auto$rtlil.cc:2443:Mux$5095, Q = \fsm_state, rval = 2'00).
Adding EN signal on $auto$ff.cc:262:slice$7688 ($sdff) from module drambone (D = $auto$rtlil.cc:2443:Mux$5095, Q = \fsm_state).
Adding SRST signal on $procdff$174 ($dff) from module fifo (D = $procmux$3320_Y, Q = \level, rval = 4'0000).
Adding EN signal on $auto$ff.cc:262:slice$7700 ($sdff) from module fifo (D = $procmux$3320_Y, Q = \level).
Adding SRST signal on $procdff$173 ($dff) from module fifo (D = $procmux$3314_Y, Q = \produce, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7704 ($sdff) from module fifo (D = $10 [2:0], Q = \produce).
Adding SRST signal on $procdff$172 ($dff) from module fifo (D = $procmux$3310_Y, Q = \consume, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7706 ($sdff) from module fifo (D = $15 [2:0], Q = \consume).
Adding SRST signal on $procdff$157 ($dff) from module fifo$13 (D = $procmux$3048_Y, Q = \level, rval = 4'0000).
Adding EN signal on $auto$ff.cc:262:slice$7708 ($sdff) from module fifo$13 (D = $procmux$3048_Y, Q = \level).
Adding SRST signal on $procdff$156 ($dff) from module fifo$13 (D = $procmux$3042_Y, Q = \produce, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7712 ($sdff) from module fifo$13 (D = $10 [2:0], Q = \produce).
Adding SRST signal on $procdff$155 ($dff) from module fifo$13 (D = $procmux$3038_Y, Q = \consume, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7714 ($sdff) from module fifo$13 (D = $15 [2:0], Q = \consume).
Adding SRST signal on $procdff$140 ($dff) from module fifo$21 (D = $procmux$2776_Y, Q = \level, rval = 4'0000).
Adding EN signal on $auto$ff.cc:262:slice$7716 ($sdff) from module fifo$21 (D = $procmux$2776_Y, Q = \level).
Adding SRST signal on $procdff$139 ($dff) from module fifo$21 (D = $procmux$2770_Y, Q = \produce, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7720 ($sdff) from module fifo$21 (D = $10 [2:0], Q = \produce).
Adding SRST signal on $procdff$138 ($dff) from module fifo$21 (D = $procmux$2766_Y, Q = \consume, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7722 ($sdff) from module fifo$21 (D = $15 [2:0], Q = \consume).
Adding SRST signal on $procdff$123 ($dff) from module fifo$29 (D = $procmux$2504_Y, Q = \level, rval = 4'0000).
Adding EN signal on $auto$ff.cc:262:slice$7724 ($sdff) from module fifo$29 (D = $procmux$2504_Y, Q = \level).
Adding SRST signal on $procdff$122 ($dff) from module fifo$29 (D = $procmux$2498_Y, Q = \produce, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7728 ($sdff) from module fifo$29 (D = $10 [2:0], Q = \produce).
Adding SRST signal on $procdff$121 ($dff) from module fifo$29 (D = $procmux$2494_Y, Q = \consume, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7730 ($sdff) from module fifo$29 (D = $15 [2:0], Q = \consume).
Adding SRST signal on $procdff$106 ($dff) from module fifo$37 (D = $procmux$2232_Y, Q = \level, rval = 4'0000).
Adding EN signal on $auto$ff.cc:262:slice$7732 ($sdff) from module fifo$37 (D = $procmux$2232_Y, Q = \level).
Adding SRST signal on $procdff$105 ($dff) from module fifo$37 (D = $procmux$2226_Y, Q = \produce, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7736 ($sdff) from module fifo$37 (D = $10 [2:0], Q = \produce).
Adding SRST signal on $procdff$104 ($dff) from module fifo$37 (D = $procmux$2222_Y, Q = \consume, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7738 ($sdff) from module fifo$37 (D = $15 [2:0], Q = \consume).
Adding SRST signal on $procdff$89 ($dff) from module fifo$45 (D = $procmux$1960_Y, Q = \level, rval = 4'0000).
Adding EN signal on $auto$ff.cc:262:slice$7740 ($sdff) from module fifo$45 (D = $procmux$1960_Y, Q = \level).
Adding SRST signal on $procdff$88 ($dff) from module fifo$45 (D = $procmux$1954_Y, Q = \produce, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7744 ($sdff) from module fifo$45 (D = $10 [2:0], Q = \produce).
Adding SRST signal on $procdff$87 ($dff) from module fifo$45 (D = $procmux$1950_Y, Q = \consume, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7746 ($sdff) from module fifo$45 (D = $15 [2:0], Q = \consume).
Adding SRST signal on $procdff$72 ($dff) from module fifo$53 (D = $procmux$1688_Y, Q = \level, rval = 4'0000).
Adding EN signal on $auto$ff.cc:262:slice$7748 ($sdff) from module fifo$53 (D = $procmux$1688_Y, Q = \level).
Adding SRST signal on $procdff$71 ($dff) from module fifo$53 (D = $procmux$1682_Y, Q = \produce, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7752 ($sdff) from module fifo$53 (D = $10 [2:0], Q = \produce).
Adding SRST signal on $procdff$70 ($dff) from module fifo$53 (D = $procmux$1678_Y, Q = \consume, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7754 ($sdff) from module fifo$53 (D = $15 [2:0], Q = \consume).
Adding SRST signal on $procdff$55 ($dff) from module fifo$61 (D = $procmux$1416_Y, Q = \level, rval = 4'0000).
Adding EN signal on $auto$ff.cc:262:slice$7756 ($sdff) from module fifo$61 (D = $procmux$1416_Y, Q = \level).
Adding SRST signal on $procdff$54 ($dff) from module fifo$61 (D = $procmux$1410_Y, Q = \produce, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7760 ($sdff) from module fifo$61 (D = $10 [2:0], Q = \produce).
Adding SRST signal on $procdff$53 ($dff) from module fifo$61 (D = $procmux$1406_Y, Q = \consume, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7762 ($sdff) from module fifo$61 (D = $15 [2:0], Q = \consume).
Adding SRST signal on $procdff$288 ($dff) from module init (D = \U$$1_lock, Q = \lock_d, rval = 1'0).
Adding SRST signal on $procdff$12 ($dff) from module multiplexer (D = $auto$rtlil.cc:2443:Mux$5211, Q = \fsm_state, rval = 4'0000).
Adding EN signal on $auto$ff.cc:262:slice$7765 ($sdff) from module multiplexer (D = $auto$rtlil.cc:2443:Mux$5211, Q = \fsm_state).
Adding SRST signal on $procdff$206 ($dff) from module phase_0 (D = $procmux$3715_Y, Q = \dfii_p0_rddata__r_data, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7783 ($sdff) from module phase_0 (D = \inti__rddata, Q = \dfii_p0_rddata__r_data).
Adding SRST signal on $procdff$205 ($dff) from module phase_1 (D = $procmux$3699_Y, Q = \dfii_p1_rddata__r_data, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7785 ($sdff) from module phase_1 (D = \inti__rddata, Q = \dfii_p1_rddata__r_data).
Adding SRST signal on $procdff$202 ($dff) from module postponer (D = $procmux$3567_Y, Q = \count, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7787 ($sdff) from module postponer (D = $procmux$3565_Y, Q = \count).
Adding SRST signal on $procdff$201 ($dff) from module postponer (D = $procmux$3558_Y, Q = \req_o, rval = 1'0).
Adding SRST signal on $procdff$16 ($dff) from module read_antistarvation (D = $procmux$537_Y, Q = \time, rval = 5'00000).
Adding EN signal on $auto$ff.cc:262:slice$7794 ($sdff) from module read_antistarvation (D = $procmux$537_Y, Q = \time).
Adding SRST signal on $procdff$15 ($dff) from module read_antistarvation (D = $procmux$531_Y, Q = \max_time, rval = 1'1).
Adding EN signal on $auto$ff.cc:262:slice$7798 ($sdff) from module read_antistarvation (D = $procmux$531_Y, Q = \max_time).
Adding SRST signal on $procdff$181 ($dff) from module refresher (D = $auto$rtlil.cc:2443:Mux$6661, Q = \fsm_state, rval = 2'00).
Adding EN signal on $auto$ff.cc:262:slice$7802 ($sdff) from module refresher (D = $auto$rtlil.cc:2443:Mux$6661, Q = \fsm_state).
Adding SRST signal on $procdff$193 ($dff) from module sequencer (D = $procmux$3497_Y, Q = \countEqZero, rval = 1'1).
Adding EN signal on $auto$ff.cc:262:slice$7816 ($sdff) from module sequencer (D = $procmux$3495_Y, Q = \countEqZero).
Adding SRST signal on $procdff$192 ($dff) from module sequencer (D = $procmux$3488_Y, Q = \countDiffZero, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7820 ($sdff) from module sequencer (D = $procmux$3486_Y, Q = \countDiffZero).
Adding SRST signal on $procdff$191 ($dff) from module sequencer (D = $procmux$3479_Y, Q = \count, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7824 ($sdff) from module sequencer (D = $procmux$3477_Y, Q = \count).
Adding SRST signal on $procdff$40 ($dff) from module steerer (D = $auto$rtlil.cc:2443:Mux$5251, Q = \mem_dfi__address$1, rval = 13'0000000000000).
Adding SRST signal on $procdff$39 ($dff) from module steerer (D = $auto$rtlil.cc:2443:Mux$5263, Q = \mem_dfi__cas$3, rval = 1'1).
Adding SRST signal on $procdff$38 ($dff) from module steerer (D = $auto$rtlil.cc:2443:Mux$5275, Q = \mem_dfi__ras$5, rval = 1'1).
Adding SRST signal on $procdff$36 ($dff) from module steerer (D = $auto$rtlil.cc:2443:Mux$5287, Q = \mem_dfi__bank, rval = 3'000).
Adding SRST signal on $procdff$35 ($dff) from module steerer (D = $auto$rtlil.cc:2443:Mux$5299, Q = \mem_dfi__address, rval = 13'0000000000000).
Adding SRST signal on $procdff$34 ($dff) from module steerer (D = $auto$rtlil.cc:2443:Mux$5311, Q = \mem_dfi__cas, rval = 1'1).
Adding SRST signal on $procdff$33 ($dff) from module steerer (D = $auto$rtlil.cc:2443:Mux$5323, Q = \mem_dfi__ras, rval = 1'1).
Adding SRST signal on $procdff$32 ($dff) from module steerer (D = $auto$rtlil.cc:2443:Mux$5335, Q = \mem_dfi__we, rval = 1'1).
Adding SRST signal on $procdff$31 ($dff) from module steerer (D = $auto$rtlil.cc:2443:Mux$5341, Q = \mem_dfi__rddata_en, rval = 1'0).
Adding SRST signal on $procdff$30 ($dff) from module steerer (D = $auto$rtlil.cc:2443:Mux$5353, Q = \mem_dfi__wrdata_en, rval = 1'0).
Adding SRST signal on $procdff$29 ($dff) from module steerer (D = $auto$rtlil.cc:2443:Mux$5371, Q = \mem_dfi__we$6, rval = 1'1).
Adding SRST signal on $procdff$28 ($dff) from module steerer (D = $auto$rtlil.cc:2443:Mux$5377, Q = \mem_dfi__rddata_en$11, rval = 1'0).
Adding SRST signal on $procdff$27 ($dff) from module steerer (D = $auto$rtlil.cc:2443:Mux$5389, Q = \mem_dfi__wrdata_en$10, rval = 1'0).
Adding SRST signal on $procdff$25 ($dff) from module steerer (D = $auto$rtlil.cc:2443:Mux$5407, Q = \mem_dfi__bank$2, rval = 3'000).
Adding EN signal on $procdff$312 ($dff) from module sysclk (D = $3 [2:0], Q = \podcnt).
Adding SRST signal on $procdff$20 ($dff) from module tccdcon (D = $procmux$565_Y, Q = \count, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7859 ($sdff) from module tccdcon (D = $procmux$565_Y, Q = \count).
Adding SRST signal on $procdff$19 ($dff) from module tccdcon (D = $procmux$557_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$22 ($dff) from module tfawcon (D = { \window [3:0] \valid }, Q = \window, rval = 5'00000).
Adding SRST signal on $procdff$21 ($dff) from module tfawcon (D = $procmux$572_Y, Q = \ready, rval = 1'1).
Adding EN signal on $auto$ff.cc:262:slice$7867 ($sdff) from module tfawcon (D = $procmux$570_Y, Q = \ready).
Adding SRST signal on $procdff$200 ($dff) from module timeline (D = $procmux$3549_Y, Q = \counter, rval = 7'0000000).
Adding EN signal on $auto$ff.cc:262:slice$7869 ($sdff) from module timeline (D = $procmux$3549_Y, Q = \counter).
Adding SRST signal on $procdff$199 ($dff) from module timeline (D = $procmux$3539_Y, Q = \a, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7875 ($sdff) from module timeline (D = 13'0010000000000, Q = \a).
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$7878 ($sdffe) from module timeline.
Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$7878 ($sdffe) from module timeline.
Setting constant 0-bit at position 2 on $auto$ff.cc:262:slice$7878 ($sdffe) from module timeline.
Setting constant 0-bit at position 3 on $auto$ff.cc:262:slice$7878 ($sdffe) from module timeline.
Setting constant 0-bit at position 4 on $auto$ff.cc:262:slice$7878 ($sdffe) from module timeline.
Setting constant 0-bit at position 5 on $auto$ff.cc:262:slice$7878 ($sdffe) from module timeline.
Setting constant 0-bit at position 6 on $auto$ff.cc:262:slice$7878 ($sdffe) from module timeline.
Setting constant 0-bit at position 7 on $auto$ff.cc:262:slice$7878 ($sdffe) from module timeline.
Setting constant 0-bit at position 8 on $auto$ff.cc:262:slice$7878 ($sdffe) from module timeline.
Setting constant 0-bit at position 9 on $auto$ff.cc:262:slice$7878 ($sdffe) from module timeline.
Setting constant 0-bit at position 11 on $auto$ff.cc:262:slice$7878 ($sdffe) from module timeline.
Setting constant 0-bit at position 12 on $auto$ff.cc:262:slice$7878 ($sdffe) from module timeline.
Adding SRST signal on $procdff$198 ($dff) from module timeline (D = $procmux$3531_Y, Q = \ba, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7880 ($sdff) from module timeline (D = 3'000, Q = \ba).
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$7883 ($sdffe) from module timeline.
Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$7883 ($sdffe) from module timeline.
Setting constant 0-bit at position 2 on $auto$ff.cc:262:slice$7883 ($sdffe) from module timeline.
Adding SRST signal on $procdff$197 ($dff) from module timeline (D = $procmux$3525_Y, Q = \cas, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7884 ($sdff) from module timeline (D = $procmux$3525_Y, Q = \cas).
Adding SRST signal on $procdff$196 ($dff) from module timeline (D = $procmux$3517_Y, Q = \ras, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7890 ($sdff) from module timeline (D = $procmux$3517_Y, Q = \ras).
Adding SRST signal on $procdff$195 ($dff) from module timeline (D = $procmux$3507_Y, Q = \we, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7896 ($sdff) from module timeline (D = 1'1, Q = \we).
Adding SRST signal on $procdff$194 ($dff) from module timeline (D = $procmux$3503_Y, Q = \done, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7900 ($sdff) from module timeline (D = 1'1, Q = \done).
Adding SRST signal on $procdff$188 ($dff) from module timeline$5 (D = $procmux$3458_Y, Q = \counter, rval = 6'000000).
Adding EN signal on $auto$ff.cc:262:slice$7902 ($sdff) from module timeline$5 (D = $procmux$3458_Y, Q = \counter).
Adding SRST signal on $procdff$187 ($dff) from module timeline$5 (D = $procmux$3448_Y, Q = \a, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:262:slice$7908 ($sdff) from module timeline$5 (D = 13'0010000000000, Q = \a).
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$7911 ($sdffe) from module timeline$5.
Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$7911 ($sdffe) from module timeline$5.
Setting constant 0-bit at position 2 on $auto$ff.cc:262:slice$7911 ($sdffe) from module timeline$5.
Setting constant 0-bit at position 3 on $auto$ff.cc:262:slice$7911 ($sdffe) from module timeline$5.
Setting constant 0-bit at position 4 on $auto$ff.cc:262:slice$7911 ($sdffe) from module timeline$5.
Setting constant 0-bit at position 5 on $auto$ff.cc:262:slice$7911 ($sdffe) from module timeline$5.
Setting constant 0-bit at position 6 on $auto$ff.cc:262:slice$7911 ($sdffe) from module timeline$5.
Setting constant 0-bit at position 7 on $auto$ff.cc:262:slice$7911 ($sdffe) from module timeline$5.
Setting constant 0-bit at position 8 on $auto$ff.cc:262:slice$7911 ($sdffe) from module timeline$5.
Setting constant 0-bit at position 9 on $auto$ff.cc:262:slice$7911 ($sdffe) from module timeline$5.
Setting constant 0-bit at position 11 on $auto$ff.cc:262:slice$7911 ($sdffe) from module timeline$5.
Setting constant 0-bit at position 12 on $auto$ff.cc:262:slice$7911 ($sdffe) from module timeline$5.
Adding SRST signal on $procdff$186 ($dff) from module timeline$5 (D = $procmux$3440_Y, Q = \ba, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$7913 ($sdff) from module timeline$5 (D = 3'000, Q = \ba).
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$7916 ($sdffe) from module timeline$5.
Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$7916 ($sdffe) from module timeline$5.
Setting constant 0-bit at position 2 on $auto$ff.cc:262:slice$7916 ($sdffe) from module timeline$5.
Adding SRST signal on $procdff$185 ($dff) from module timeline$5 (D = $procmux$3432_Y, Q = \cas, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7917 ($sdff) from module timeline$5 (D = 1'0, Q = \cas).
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$7920 ($sdffe) from module timeline$5.
Adding SRST signal on $procdff$184 ($dff) from module timeline$5 (D = $procmux$3424_Y, Q = \ras, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7921 ($sdff) from module timeline$5 (D = 1'1, Q = \ras).
Adding SRST signal on $procdff$183 ($dff) from module timeline$5 (D = $procmux$3418_Y, Q = \we, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7925 ($sdff) from module timeline$5 (D = $procmux$3418_Y, Q = \we).
Adding SRST signal on $procdff$182 ($dff) from module timeline$5 (D = $procmux$3412_Y, Q = \done, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7931 ($sdff) from module timeline$5 (D = $procmux$3412_Y, Q = \done).
Adding SRST signal on $procdff$204 ($dff) from module timer (D = $5 [9:0], Q = \count, rval = 10'1100001101).
Adding SRST signal on $procdff$203 ($dff) from module timer (D = $procmux$3572_Y, Q = \done, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$7940 ($sdff) from module timer (D = 1'1, Q = \done).
Adding SRST signal on $procdff$176 ($dff) from module trascon (D = $procmux$3334_Y, Q = \count, rval = 2'00).
Adding EN signal on $auto$ff.cc:262:slice$7946 ($sdff) from module trascon (D = $procmux$3334_Y, Q = \count).
Adding SRST signal on $procdff$175 ($dff) from module trascon (D = $procmux$3326_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$159 ($dff) from module trascon$11 (D = $procmux$3062_Y, Q = \count, rval = 2'00).
Adding EN signal on $auto$ff.cc:262:slice$7953 ($sdff) from module trascon$11 (D = $procmux$3062_Y, Q = \count).
Adding SRST signal on $procdff$158 ($dff) from module trascon$11 (D = $procmux$3054_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$142 ($dff) from module trascon$19 (D = $procmux$2790_Y, Q = \count, rval = 2'00).
Adding EN signal on $auto$ff.cc:262:slice$7960 ($sdff) from module trascon$19 (D = $procmux$2790_Y, Q = \count).
Adding SRST signal on $procdff$141 ($dff) from module trascon$19 (D = $procmux$2782_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$125 ($dff) from module trascon$27 (D = $procmux$2518_Y, Q = \count, rval = 2'00).
Adding EN signal on $auto$ff.cc:262:slice$7967 ($sdff) from module trascon$27 (D = $procmux$2518_Y, Q = \count).
Adding SRST signal on $procdff$124 ($dff) from module trascon$27 (D = $procmux$2510_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$108 ($dff) from module trascon$35 (D = $procmux$2246_Y, Q = \count, rval = 2'00).
Adding EN signal on $auto$ff.cc:262:slice$7974 ($sdff) from module trascon$35 (D = $procmux$2246_Y, Q = \count).
Adding SRST signal on $procdff$107 ($dff) from module trascon$35 (D = $procmux$2238_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$91 ($dff) from module trascon$43 (D = $procmux$1974_Y, Q = \count, rval = 2'00).
Adding EN signal on $auto$ff.cc:262:slice$7981 ($sdff) from module trascon$43 (D = $procmux$1974_Y, Q = \count).
Adding SRST signal on $procdff$90 ($dff) from module trascon$43 (D = $procmux$1966_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$74 ($dff) from module trascon$51 (D = $procmux$1702_Y, Q = \count, rval = 2'00).
Adding EN signal on $auto$ff.cc:262:slice$7988 ($sdff) from module trascon$51 (D = $procmux$1702_Y, Q = \count).
Adding SRST signal on $procdff$73 ($dff) from module trascon$51 (D = $procmux$1694_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$57 ($dff) from module trascon$59 (D = $procmux$1430_Y, Q = \count, rval = 2'00).
Adding EN signal on $auto$ff.cc:262:slice$7995 ($sdff) from module trascon$59 (D = $procmux$1430_Y, Q = \count).
Adding SRST signal on $procdff$56 ($dff) from module trascon$59 (D = $procmux$1422_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$178 ($dff) from module trccon (D = { $procmux$3348_Y [2] $procmux$3348_Y [0] }, Q = { \count [2] \count [0] }, rval = 2'00).
Adding SRST signal on $procdff$178 ($dff) from module trccon (D = $procmux$3346_Y [1], Q = \count [1], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8003 ($sdff) from module trccon (D = $3 [1], Q = \count [1]).
Adding EN signal on $auto$ff.cc:262:slice$8002 ($sdff) from module trccon (D = { $procmux$3348_Y [2] $procmux$3348_Y [0] }, Q = { \count [2] \count [0] }).
Adding SRST signal on $procdff$177 ($dff) from module trccon (D = $procmux$3340_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$161 ($dff) from module trccon$10 (D = { $procmux$3076_Y [2] $procmux$3076_Y [0] }, Q = { \count [2] \count [0] }, rval = 2'00).
Adding SRST signal on $procdff$161 ($dff) from module trccon$10 (D = $procmux$3074_Y [1], Q = \count [1], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8014 ($sdff) from module trccon$10 (D = $3 [1], Q = \count [1]).
Adding EN signal on $auto$ff.cc:262:slice$8013 ($sdff) from module trccon$10 (D = { $procmux$3076_Y [2] $procmux$3076_Y [0] }, Q = { \count [2] \count [0] }).
Adding SRST signal on $procdff$160 ($dff) from module trccon$10 (D = $procmux$3068_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$144 ($dff) from module trccon$18 (D = { $procmux$2804_Y [2] $procmux$2804_Y [0] }, Q = { \count [2] \count [0] }, rval = 2'00).
Adding SRST signal on $procdff$144 ($dff) from module trccon$18 (D = $procmux$2802_Y [1], Q = \count [1], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8025 ($sdff) from module trccon$18 (D = $3 [1], Q = \count [1]).
Adding EN signal on $auto$ff.cc:262:slice$8024 ($sdff) from module trccon$18 (D = { $procmux$2804_Y [2] $procmux$2804_Y [0] }, Q = { \count [2] \count [0] }).
Adding SRST signal on $procdff$143 ($dff) from module trccon$18 (D = $procmux$2796_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$127 ($dff) from module trccon$26 (D = { $procmux$2532_Y [2] $procmux$2532_Y [0] }, Q = { \count [2] \count [0] }, rval = 2'00).
Adding SRST signal on $procdff$127 ($dff) from module trccon$26 (D = $procmux$2530_Y [1], Q = \count [1], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8036 ($sdff) from module trccon$26 (D = $3 [1], Q = \count [1]).
Adding EN signal on $auto$ff.cc:262:slice$8035 ($sdff) from module trccon$26 (D = { $procmux$2532_Y [2] $procmux$2532_Y [0] }, Q = { \count [2] \count [0] }).
Adding SRST signal on $procdff$126 ($dff) from module trccon$26 (D = $procmux$2524_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$110 ($dff) from module trccon$34 (D = { $procmux$2260_Y [2] $procmux$2260_Y [0] }, Q = { \count [2] \count [0] }, rval = 2'00).
Adding SRST signal on $procdff$110 ($dff) from module trccon$34 (D = $procmux$2258_Y [1], Q = \count [1], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8047 ($sdff) from module trccon$34 (D = $3 [1], Q = \count [1]).
Adding EN signal on $auto$ff.cc:262:slice$8046 ($sdff) from module trccon$34 (D = { $procmux$2260_Y [2] $procmux$2260_Y [0] }, Q = { \count [2] \count [0] }).
Adding SRST signal on $procdff$109 ($dff) from module trccon$34 (D = $procmux$2252_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$93 ($dff) from module trccon$42 (D = { $procmux$1988_Y [2] $procmux$1988_Y [0] }, Q = { \count [2] \count [0] }, rval = 2'00).
Adding SRST signal on $procdff$93 ($dff) from module trccon$42 (D = $procmux$1986_Y [1], Q = \count [1], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8058 ($sdff) from module trccon$42 (D = $3 [1], Q = \count [1]).
Adding EN signal on $auto$ff.cc:262:slice$8057 ($sdff) from module trccon$42 (D = { $procmux$1988_Y [2] $procmux$1988_Y [0] }, Q = { \count [2] \count [0] }).
Adding SRST signal on $procdff$92 ($dff) from module trccon$42 (D = $procmux$1980_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$76 ($dff) from module trccon$50 (D = { $procmux$1716_Y [2] $procmux$1716_Y [0] }, Q = { \count [2] \count [0] }, rval = 2'00).
Adding SRST signal on $procdff$76 ($dff) from module trccon$50 (D = $procmux$1714_Y [1], Q = \count [1], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8069 ($sdff) from module trccon$50 (D = $3 [1], Q = \count [1]).
Adding EN signal on $auto$ff.cc:262:slice$8068 ($sdff) from module trccon$50 (D = { $procmux$1716_Y [2] $procmux$1716_Y [0] }, Q = { \count [2] \count [0] }).
Adding SRST signal on $procdff$75 ($dff) from module trccon$50 (D = $procmux$1708_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$59 ($dff) from module trccon$58 (D = { $procmux$1444_Y [2] $procmux$1444_Y [0] }, Q = { \count [2] \count [0] }, rval = 2'00).
Adding SRST signal on $procdff$59 ($dff) from module trccon$58 (D = $procmux$1442_Y [1], Q = \count [1], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8080 ($sdff) from module trccon$58 (D = $3 [1], Q = \count [1]).
Adding EN signal on $auto$ff.cc:262:slice$8079 ($sdff) from module trccon$58 (D = { $procmux$1444_Y [2] $procmux$1444_Y [0] }, Q = { \count [2] \count [0] }).
Adding SRST signal on $procdff$58 ($dff) from module trccon$58 (D = $procmux$1436_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$24 ($dff) from module trrdcon (D = $procmux$588_Y, Q = \count, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8090 ($sdff) from module trrdcon (D = $procmux$588_Y, Q = \count).
Adding SRST signal on $procdff$23 ($dff) from module trrdcon (D = $procmux$580_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$180 ($dff) from module twtpcon (D = $procmux$3362_Y [2:1], Q = \count [2:1], rval = 2'00).
Adding SRST signal on $procdff$180 ($dff) from module twtpcon (D = $procmux$3360_Y [0], Q = \count [0], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8098 ($sdff) from module twtpcon (D = $3 [0], Q = \count [0]).
Adding EN signal on $auto$ff.cc:262:slice$8097 ($sdff) from module twtpcon (D = $procmux$3362_Y [2:1], Q = \count [2:1]).
Adding SRST signal on $procdff$179 ($dff) from module twtpcon (D = $procmux$3354_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$146 ($dff) from module twtpcon$17 (D = $procmux$2818_Y [2:1], Q = \count [2:1], rval = 2'00).
Adding SRST signal on $procdff$146 ($dff) from module twtpcon$17 (D = $procmux$2816_Y [0], Q = \count [0], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8109 ($sdff) from module twtpcon$17 (D = $3 [0], Q = \count [0]).
Adding EN signal on $auto$ff.cc:262:slice$8108 ($sdff) from module twtpcon$17 (D = $procmux$2818_Y [2:1], Q = \count [2:1]).
Adding SRST signal on $procdff$145 ($dff) from module twtpcon$17 (D = $procmux$2810_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$129 ($dff) from module twtpcon$25 (D = $procmux$2546_Y [2:1], Q = \count [2:1], rval = 2'00).
Adding SRST signal on $procdff$129 ($dff) from module twtpcon$25 (D = $procmux$2544_Y [0], Q = \count [0], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8120 ($sdff) from module twtpcon$25 (D = $3 [0], Q = \count [0]).
Adding EN signal on $auto$ff.cc:262:slice$8119 ($sdff) from module twtpcon$25 (D = $procmux$2546_Y [2:1], Q = \count [2:1]).
Adding SRST signal on $procdff$128 ($dff) from module twtpcon$25 (D = $procmux$2538_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$112 ($dff) from module twtpcon$33 (D = $procmux$2274_Y [2:1], Q = \count [2:1], rval = 2'00).
Adding SRST signal on $procdff$112 ($dff) from module twtpcon$33 (D = $procmux$2272_Y [0], Q = \count [0], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8131 ($sdff) from module twtpcon$33 (D = $3 [0], Q = \count [0]).
Adding EN signal on $auto$ff.cc:262:slice$8130 ($sdff) from module twtpcon$33 (D = $procmux$2274_Y [2:1], Q = \count [2:1]).
Adding SRST signal on $procdff$111 ($dff) from module twtpcon$33 (D = $procmux$2266_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$95 ($dff) from module twtpcon$41 (D = $procmux$2002_Y [2:1], Q = \count [2:1], rval = 2'00).
Adding SRST signal on $procdff$95 ($dff) from module twtpcon$41 (D = $procmux$2000_Y [0], Q = \count [0], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8142 ($sdff) from module twtpcon$41 (D = $3 [0], Q = \count [0]).
Adding EN signal on $auto$ff.cc:262:slice$8141 ($sdff) from module twtpcon$41 (D = $procmux$2002_Y [2:1], Q = \count [2:1]).
Adding SRST signal on $procdff$94 ($dff) from module twtpcon$41 (D = $procmux$1994_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$78 ($dff) from module twtpcon$49 (D = $procmux$1730_Y [2:1], Q = \count [2:1], rval = 2'00).
Adding SRST signal on $procdff$78 ($dff) from module twtpcon$49 (D = $procmux$1728_Y [0], Q = \count [0], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8153 ($sdff) from module twtpcon$49 (D = $3 [0], Q = \count [0]).
Adding EN signal on $auto$ff.cc:262:slice$8152 ($sdff) from module twtpcon$49 (D = $procmux$1730_Y [2:1], Q = \count [2:1]).
Adding SRST signal on $procdff$77 ($dff) from module twtpcon$49 (D = $procmux$1722_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$61 ($dff) from module twtpcon$57 (D = $procmux$1458_Y [2:1], Q = \count [2:1], rval = 2'00).
Adding SRST signal on $procdff$61 ($dff) from module twtpcon$57 (D = $procmux$1456_Y [0], Q = \count [0], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8164 ($sdff) from module twtpcon$57 (D = $3 [0], Q = \count [0]).
Adding EN signal on $auto$ff.cc:262:slice$8163 ($sdff) from module twtpcon$57 (D = $procmux$1458_Y [2:1], Q = \count [2:1]).
Adding SRST signal on $procdff$60 ($dff) from module twtpcon$57 (D = $procmux$1450_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$163 ($dff) from module twtpcon$9 (D = $procmux$3090_Y [2:1], Q = \count [2:1], rval = 2'00).
Adding SRST signal on $procdff$163 ($dff) from module twtpcon$9 (D = $procmux$3088_Y [0], Q = \count [0], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8175 ($sdff) from module twtpcon$9 (D = $3 [0], Q = \count [0]).
Adding EN signal on $auto$ff.cc:262:slice$8174 ($sdff) from module twtpcon$9 (D = $procmux$3090_Y [2:1], Q = \count [2:1]).
Adding SRST signal on $procdff$162 ($dff) from module twtpcon$9 (D = $procmux$3082_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$18 ($dff) from module twtrcon (D = $procmux$551_Y [2:1], Q = \count [2:1], rval = 2'00).
Adding SRST signal on $procdff$18 ($dff) from module twtrcon (D = $procmux$549_Y [0], Q = \count [0], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8186 ($sdff) from module twtrcon (D = $3 [0], Q = \count [0]).
Adding EN signal on $auto$ff.cc:262:slice$8185 ($sdff) from module twtrcon (D = $procmux$551_Y [2:1], Q = \count [2:1]).
Adding SRST signal on $procdff$17 ($dff) from module twtrcon (D = $procmux$543_Y, Q = \ready, rval = 1'0).
Adding SRST signal on $procdff$14 ($dff) from module write_antistarvation (D = $procmux$522_Y, Q = \time, rval = 4'0000).
Adding EN signal on $auto$ff.cc:262:slice$8196 ($sdff) from module write_antistarvation (D = $procmux$522_Y, Q = \time).
Adding SRST signal on $procdff$13 ($dff) from module write_antistarvation (D = $procmux$516_Y, Q = \max_time, rval = 1'1).
Adding EN signal on $auto$ff.cc:262:slice$8200 ($sdff) from module write_antistarvation (D = $procmux$516_Y, Q = \max_time).
Adding SRST signal on $procdff$190 ($dff) from module zqcs_timer (D = $5 [26:0], Q = \count, rval = 27'101111101011110000011111111).
Adding SRST signal on $procdff$189 ($dff) from module zqcs_timer (D = $procmux$3466_Y, Q = \done, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$8209 ($sdff) from module zqcs_timer (D = 1'1, Q = \done).

15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \U$$0..
Finding unused cells or wires in module \U$$0$12..
Finding unused cells or wires in module \U$$0$20..
Finding unused cells or wires in module \U$$0$28..
Finding unused cells or wires in module \U$$0$36..
Finding unused cells or wires in module \U$$0$44..
Finding unused cells or wires in module \U$$0$52..
Finding unused cells or wires in module \U$$0$60..
Finding unused cells or wires in module \U$$0$64..
Finding unused cells or wires in module \U$$1..
Finding unused cells or wires in module \U$$1$14..
Finding unused cells or wires in module \U$$1$22..
Finding unused cells or wires in module \U$$1$30..
Finding unused cells or wires in module \U$$1$38..
Finding unused cells or wires in module \U$$1$46..
Finding unused cells or wires in module \U$$1$54..
Finding unused cells or wires in module \U$$1$6..
Finding unused cells or wires in module \U$$1$62..
Finding unused cells or wires in module \U$$1$65..
Finding unused cells or wires in module \U$$2..
Finding unused cells or wires in module \U$$2$66..
Finding unused cells or wires in module \U$$3..
Finding unused cells or wires in module \U$$4..
Finding unused cells or wires in module \U$$5..
Finding unused cells or wires in module \U$$6..
Finding unused cells or wires in module \U$$7..
Finding unused cells or wires in module \U$$8..
Finding unused cells or wires in module \U$$9..
Finding unused cells or wires in module \arbiter..
Finding unused cells or wires in module \arbiter$63..
Finding unused cells or wires in module \bankmachine0..
Finding unused cells or wires in module \bankmachine1..
Finding unused cells or wires in module \bankmachine2..
Finding unused cells or wires in module \bankmachine3..
Finding unused cells or wires in module \bankmachine4..
Finding unused cells or wires in module \bankmachine5..
Finding unused cells or wires in module \bankmachine6..
Finding unused cells or wires in module \bankmachine7..
Finding unused cells or wires in module \bridge..
Finding unused cells or wires in module \bridge$1..
Finding unused cells or wires in module \choose_cmd..
Finding unused cells or wires in module \choose_req..
Finding unused cells or wires in module \controller..
Finding unused cells or wires in module \crossbar..
Finding unused cells or wires in module \csr_bridge_0..
Finding unused cells or wires in module \csr_bridge_0$3..
Finding unused cells or wires in module \csr_mux_0..
Finding unused cells or wires in module \csr_mux_0$2..
Finding unused cells or wires in module \current_slicer..
Finding unused cells or wires in module \current_slicer$16..
Finding unused cells or wires in module \current_slicer$24..
Finding unused cells or wires in module \current_slicer$32..
Finding unused cells or wires in module \current_slicer$40..
Finding unused cells or wires in module \current_slicer$48..
Finding unused cells or wires in module \current_slicer$56..
Finding unused cells or wires in module \current_slicer$8..
Finding unused cells or wires in module \ddrphy..
Finding unused cells or wires in module \decoder..
Finding unused cells or wires in module \dfii..
Finding unused cells or wires in module \dqsbufm_manager0..
Finding unused cells or wires in module \dqsbufm_manager1..
Finding unused cells or wires in module \drambone..
Finding unused cells or wires in module \dramcore..
Finding unused cells or wires in module \executer..
Finding unused cells or wires in module \fifo..
Finding unused cells or wires in module \fifo$13..
Finding unused cells or wires in module \fifo$21..
Finding unused cells or wires in module \fifo$29..
Finding unused cells or wires in module \fifo$37..
Finding unused cells or wires in module \fifo$45..
Finding unused cells or wires in module \fifo$53..
Finding unused cells or wires in module \fifo$61..
Finding unused cells or wires in module \init..
Finding unused cells or wires in module \lookahead_slicer..
Finding unused cells or wires in module \lookahead_slicer$15..
Finding unused cells or wires in module \lookahead_slicer$23..
Finding unused cells or wires in module \lookahead_slicer$31..
Finding unused cells or wires in module \lookahead_slicer$39..
Finding unused cells or wires in module \lookahead_slicer$47..
Finding unused cells or wires in module \lookahead_slicer$55..
Finding unused cells or wires in module \lookahead_slicer$7..
Finding unused cells or wires in module \multiplexer..
Finding unused cells or wires in module \phase_0..
Finding unused cells or wires in module \phase_1..
Finding unused cells or wires in module \pin_clk100_0..
Finding unused cells or wires in module \pin_ddr3_0__a..
Finding unused cells or wires in module \pin_ddr3_0__ba..
Finding unused cells or wires in module \pin_ddr3_0__cas..
Finding unused cells or wires in module \pin_ddr3_0__clk..
Finding unused cells or wires in module \pin_ddr3_0__clk_en..
Finding unused cells or wires in module \pin_ddr3_0__cs..
Finding unused cells or wires in module \pin_ddr3_0__dm..
Finding unused cells or wires in module \pin_ddr3_0__odt..
Finding unused cells or wires in module \pin_ddr3_0__ras..
Finding unused cells or wires in module \pin_ddr3_0__rst..
Finding unused cells or wires in module \pin_ddr3_0__we..
Finding unused cells or wires in module \pin_rst_0..
Finding unused cells or wires in module \pin_wishbone_0__ack..
Finding unused cells or wires in module \pin_wishbone_0__adr..
Finding unused cells or wires in module \pin_wishbone_0__cyc..
Finding unused cells or wires in module \pin_wishbone_0__dat_r..
Finding unused cells or wires in module \pin_wishbone_0__dat_w..
Finding unused cells or wires in module \pin_wishbone_0__sel..
Finding unused cells or wires in module \pin_wishbone_0__stb..
Finding unused cells or wires in module \pin_wishbone_0__we..
Finding unused cells or wires in module \pll..
Finding unused cells or wires in module \postponer..
Finding unused cells or wires in module \read_antistarvation..
Finding unused cells or wires in module \refresher..
Finding unused cells or wires in module \sequencer..
Finding unused cells or wires in module \steerer..
Finding unused cells or wires in module \sysclk..
Finding unused cells or wires in module \tccdcon..
Finding unused cells or wires in module \tfawcon..
Finding unused cells or wires in module \timeline..
Finding unused cells or wires in module \timeline$5..
Finding unused cells or wires in module \timer..
Finding unused cells or wires in module \top..
Finding unused cells or wires in module \trascon..
Finding unused cells or wires in module \trascon$11..
Finding unused cells or wires in module \trascon$19..
Finding unused cells or wires in module \trascon$27..
Finding unused cells or wires in module \trascon$35..
Finding unused cells or wires in module \trascon$43..
Finding unused cells or wires in module \trascon$51..
Finding unused cells or wires in module \trascon$59..
Finding unused cells or wires in module \trccon..
Finding unused cells or wires in module \trccon$10..
Finding unused cells or wires in module \trccon$18..
Finding unused cells or wires in module \trccon$26..
Finding unused cells or wires in module \trccon$34..
Finding unused cells or wires in module \trccon$42..
Finding unused cells or wires in module \trccon$50..
Finding unused cells or wires in module \trccon$58..
Finding unused cells or wires in module \trrdcon..
Finding unused cells or wires in module \twtpcon..
Finding unused cells or wires in module \twtpcon$17..
Finding unused cells or wires in module \twtpcon$25..
Finding unused cells or wires in module \twtpcon$33..
Finding unused cells or wires in module \twtpcon$41..
Finding unused cells or wires in module \twtpcon$49..
Finding unused cells or wires in module \twtpcon$57..
Finding unused cells or wires in module \twtpcon$9..
Finding unused cells or wires in module \twtrcon..
Finding unused cells or wires in module \wb_decoder..
Finding unused cells or wires in module \wb_decoder$4..
Finding unused cells or wires in module \write_antistarvation..
Finding unused cells or wires in module \zqcs_executer..
Finding unused cells or wires in module \zqcs_timer..
Removed 965 unused cells and 2513 unused wires.
<suppressed ~1291 debug messages>

15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module U$$0.
Optimizing module U$$0$12.
Optimizing module U$$0$20.
Optimizing module U$$0$28.
Optimizing module U$$0$36.
Optimizing module U$$0$44.
Optimizing module U$$0$52.
Optimizing module U$$0$60.
Optimizing module U$$0$64.
Optimizing module U$$1.
Optimizing module U$$1$14.
Optimizing module U$$1$22.
Optimizing module U$$1$30.
Optimizing module U$$1$38.
Optimizing module U$$1$46.
Optimizing module U$$1$54.
Optimizing module U$$1$6.
Optimizing module U$$1$62.
Optimizing module U$$1$65.
Optimizing module U$$2.
<suppressed ~1 debug messages>
Optimizing module U$$2$66.
Optimizing module U$$3.
Optimizing module U$$4.
Optimizing module U$$5.
Optimizing module U$$6.
Optimizing module U$$7.
Optimizing module U$$8.
Optimizing module U$$9.
Optimizing module arbiter.
<suppressed ~1 debug messages>
Optimizing module arbiter$63.
<suppressed ~1 debug messages>
Optimizing module bankmachine0.
<suppressed ~2 debug messages>
Optimizing module bankmachine1.
<suppressed ~2 debug messages>
Optimizing module bankmachine2.
<suppressed ~2 debug messages>
Optimizing module bankmachine3.
<suppressed ~2 debug messages>
Optimizing module bankmachine4.
<suppressed ~2 debug messages>
Optimizing module bankmachine5.
<suppressed ~2 debug messages>
Optimizing module bankmachine6.
<suppressed ~2 debug messages>
Optimizing module bankmachine7.
<suppressed ~2 debug messages>
Optimizing module bridge.
Optimizing module bridge$1.
Optimizing module choose_cmd.
Optimizing module choose_req.
Optimizing module controller.
Optimizing module crossbar.
Optimizing module csr_bridge_0.
<suppressed ~1 debug messages>
Optimizing module csr_bridge_0$3.
<suppressed ~1 debug messages>
Optimizing module csr_mux_0.
<suppressed ~4 debug messages>
Optimizing module csr_mux_0$2.
Optimizing module current_slicer.
Optimizing module current_slicer$16.
Optimizing module current_slicer$24.
Optimizing module current_slicer$32.
Optimizing module current_slicer$40.
Optimizing module current_slicer$48.
Optimizing module current_slicer$56.
Optimizing module current_slicer$8.
Optimizing module ddrphy.
Optimizing module decoder.
Optimizing module dfii.
Optimizing module dqsbufm_manager0.
<suppressed ~1 debug messages>
Optimizing module dqsbufm_manager1.
<suppressed ~1 debug messages>
Optimizing module drambone.
<suppressed ~1 debug messages>
Optimizing module dramcore.
Optimizing module executer.
Optimizing module fifo.
<suppressed ~1 debug messages>
Optimizing module fifo$13.
<suppressed ~1 debug messages>
Optimizing module fifo$21.
<suppressed ~1 debug messages>
Optimizing module fifo$29.
<suppressed ~1 debug messages>
Optimizing module fifo$37.
<suppressed ~1 debug messages>
Optimizing module fifo$45.
<suppressed ~1 debug messages>
Optimizing module fifo$53.
<suppressed ~1 debug messages>
Optimizing module fifo$61.
<suppressed ~1 debug messages>
Optimizing module init.
Optimizing module lookahead_slicer.
Optimizing module lookahead_slicer$15.
Optimizing module lookahead_slicer$23.
Optimizing module lookahead_slicer$31.
Optimizing module lookahead_slicer$39.
Optimizing module lookahead_slicer$47.
Optimizing module lookahead_slicer$55.
Optimizing module lookahead_slicer$7.
Optimizing module multiplexer.
<suppressed ~1 debug messages>
Optimizing module phase_0.
Optimizing module phase_1.
Optimizing module pin_clk100_0.
Optimizing module pin_ddr3_0__a.
Optimizing module pin_ddr3_0__ba.
Optimizing module pin_ddr3_0__cas.
Optimizing module pin_ddr3_0__clk.
Optimizing module pin_ddr3_0__clk_en.
Optimizing module pin_ddr3_0__cs.
Optimizing module pin_ddr3_0__dm.
Optimizing module pin_ddr3_0__odt.
Optimizing module pin_ddr3_0__ras.
Optimizing module pin_ddr3_0__rst.
Optimizing module pin_ddr3_0__we.
Optimizing module pin_rst_0.
Optimizing module pin_wishbone_0__ack.
Optimizing module pin_wishbone_0__adr.
Optimizing module pin_wishbone_0__cyc.
Optimizing module pin_wishbone_0__dat_r.
Optimizing module pin_wishbone_0__dat_w.
Optimizing module pin_wishbone_0__sel.
Optimizing module pin_wishbone_0__stb.
Optimizing module pin_wishbone_0__we.
Optimizing module pll.
Optimizing module postponer.
Optimizing module read_antistarvation.
Optimizing module refresher.
<suppressed ~1 debug messages>
Optimizing module sequencer.
Optimizing module steerer.
Optimizing module sysclk.
Optimizing module tccdcon.
Optimizing module tfawcon.
Optimizing module timeline.
<suppressed ~3 debug messages>
Optimizing module timeline$5.
<suppressed ~3 debug messages>
Optimizing module timer.
Optimizing module top.
Optimizing module trascon.
Optimizing module trascon$11.
Optimizing module trascon$19.
Optimizing module trascon$27.
Optimizing module trascon$35.
Optimizing module trascon$43.
Optimizing module trascon$51.
Optimizing module trascon$59.
Optimizing module trccon.
Optimizing module trccon$10.
Optimizing module trccon$18.
Optimizing module trccon$26.
Optimizing module trccon$34.
Optimizing module trccon$42.
Optimizing module trccon$50.
Optimizing module trccon$58.
Optimizing module trrdcon.
Optimizing module twtpcon.
Optimizing module twtpcon$17.
Optimizing module twtpcon$25.
Optimizing module twtpcon$33.
Optimizing module twtpcon$41.
Optimizing module twtpcon$49.
Optimizing module twtpcon$57.
Optimizing module twtpcon$9.
Optimizing module twtrcon.
Optimizing module wb_decoder.
Optimizing module wb_decoder$4.
Optimizing module write_antistarvation.
Optimizing module zqcs_executer.
Optimizing module zqcs_timer.

15.9. Rerunning OPT passes. (Maybe there is more to do..)

15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \U$$0..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$12..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$20..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$28..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$36..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$44..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$52..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$60..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$64..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$14..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$22..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$30..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$38..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$46..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$54..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$6..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$62..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$65..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$2..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \U$$2$66..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$3..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$5..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$6..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$7..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$8..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$9..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \arbiter..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \arbiter$63..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine0..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine1..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine2..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine4..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine5..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine6..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine7..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bridge..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \bridge$1..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \choose_cmd..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \choose_req..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \controller..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \crossbar..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \csr_bridge_0..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \csr_bridge_0$3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \csr_mux_0..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \csr_mux_0$2..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \current_slicer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$16..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$24..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$32..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$40..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$48..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$56..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$8..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \ddrphy..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \decoder..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \dfii..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \dqsbufm_manager0..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \dqsbufm_manager1..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \drambone..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \dramcore..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \executer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \fifo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$13..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$21..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$29..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$37..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$45..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$53..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$61..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \init..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$15..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$23..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$31..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$39..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$47..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$55..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$7..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \multiplexer..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \phase_0..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \phase_1..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \pin_clk100_0..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__a..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__ba..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__cas..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__clk..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__clk_en..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__cs..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__dm..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__odt..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__ras..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__rst..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__we..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_rst_0..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__ack..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__adr..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__cyc..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__dat_r..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__dat_w..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__sel..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__stb..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__we..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pll..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \postponer..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \read_antistarvation..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \refresher..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \sequencer..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \steerer..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \sysclk..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \tccdcon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \tfawcon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \timeline..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \timeline$5..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \timer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \trascon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$11..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$19..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$27..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$35..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$43..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$51..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$59..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$10..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$18..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$26..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$34..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$42..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$50..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$58..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trrdcon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$17..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$25..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$33..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$41..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$49..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$57..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$9..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtrcon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \wb_decoder..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \wb_decoder$4..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \write_antistarvation..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \zqcs_executer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \zqcs_timer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.
<suppressed ~417 debug messages>

15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \U$$0.
  Optimizing cells in module \U$$0$12.
  Optimizing cells in module \U$$0$20.
  Optimizing cells in module \U$$0$28.
  Optimizing cells in module \U$$0$36.
  Optimizing cells in module \U$$0$44.
  Optimizing cells in module \U$$0$52.
  Optimizing cells in module \U$$0$60.
  Optimizing cells in module \U$$0$64.
  Optimizing cells in module \U$$1.
  Optimizing cells in module \U$$1$14.
  Optimizing cells in module \U$$1$22.
  Optimizing cells in module \U$$1$30.
  Optimizing cells in module \U$$1$38.
  Optimizing cells in module \U$$1$46.
  Optimizing cells in module \U$$1$54.
  Optimizing cells in module \U$$1$6.
  Optimizing cells in module \U$$1$62.
  Optimizing cells in module \U$$1$65.
  Optimizing cells in module \U$$2.
  Optimizing cells in module \U$$2$66.
  Optimizing cells in module \U$$3.
  Optimizing cells in module \U$$4.
  Optimizing cells in module \U$$5.
  Optimizing cells in module \U$$6.
  Optimizing cells in module \U$$7.
  Optimizing cells in module \U$$8.
  Optimizing cells in module \U$$9.
  Optimizing cells in module \arbiter.
  Optimizing cells in module \arbiter$63.
  Optimizing cells in module \bankmachine0.
  Optimizing cells in module \bankmachine1.
  Optimizing cells in module \bankmachine2.
  Optimizing cells in module \bankmachine3.
  Optimizing cells in module \bankmachine4.
  Optimizing cells in module \bankmachine5.
  Optimizing cells in module \bankmachine6.
  Optimizing cells in module \bankmachine7.
  Optimizing cells in module \bridge.
  Optimizing cells in module \bridge$1.
  Optimizing cells in module \choose_cmd.
  Optimizing cells in module \choose_req.
  Optimizing cells in module \controller.
  Optimizing cells in module \crossbar.
  Optimizing cells in module \csr_bridge_0.
  Optimizing cells in module \csr_bridge_0$3.
  Optimizing cells in module \csr_mux_0.
  Optimizing cells in module \csr_mux_0$2.
  Optimizing cells in module \current_slicer.
  Optimizing cells in module \current_slicer$16.
  Optimizing cells in module \current_slicer$24.
  Optimizing cells in module \current_slicer$32.
  Optimizing cells in module \current_slicer$40.
  Optimizing cells in module \current_slicer$48.
  Optimizing cells in module \current_slicer$56.
  Optimizing cells in module \current_slicer$8.
  Optimizing cells in module \ddrphy.
  Optimizing cells in module \decoder.
  Optimizing cells in module \dfii.
  Optimizing cells in module \dqsbufm_manager0.
  Optimizing cells in module \dqsbufm_manager1.
  Optimizing cells in module \drambone.
  Optimizing cells in module \dramcore.
  Optimizing cells in module \executer.
  Optimizing cells in module \fifo.
  Optimizing cells in module \fifo$13.
  Optimizing cells in module \fifo$21.
  Optimizing cells in module \fifo$29.
  Optimizing cells in module \fifo$37.
  Optimizing cells in module \fifo$45.
  Optimizing cells in module \fifo$53.
  Optimizing cells in module \fifo$61.
  Optimizing cells in module \init.
  Optimizing cells in module \lookahead_slicer.
  Optimizing cells in module \lookahead_slicer$15.
  Optimizing cells in module \lookahead_slicer$23.
  Optimizing cells in module \lookahead_slicer$31.
  Optimizing cells in module \lookahead_slicer$39.
  Optimizing cells in module \lookahead_slicer$47.
  Optimizing cells in module \lookahead_slicer$55.
  Optimizing cells in module \lookahead_slicer$7.
  Optimizing cells in module \multiplexer.
  Optimizing cells in module \phase_0.
  Optimizing cells in module \phase_1.
  Optimizing cells in module \pin_clk100_0.
  Optimizing cells in module \pin_ddr3_0__a.
  Optimizing cells in module \pin_ddr3_0__ba.
  Optimizing cells in module \pin_ddr3_0__cas.
  Optimizing cells in module \pin_ddr3_0__clk.
  Optimizing cells in module \pin_ddr3_0__clk_en.
  Optimizing cells in module \pin_ddr3_0__cs.
  Optimizing cells in module \pin_ddr3_0__dm.
  Optimizing cells in module \pin_ddr3_0__odt.
  Optimizing cells in module \pin_ddr3_0__ras.
  Optimizing cells in module \pin_ddr3_0__rst.
  Optimizing cells in module \pin_ddr3_0__we.
  Optimizing cells in module \pin_rst_0.
  Optimizing cells in module \pin_wishbone_0__ack.
  Optimizing cells in module \pin_wishbone_0__adr.
  Optimizing cells in module \pin_wishbone_0__cyc.
  Optimizing cells in module \pin_wishbone_0__dat_r.
  Optimizing cells in module \pin_wishbone_0__dat_w.
  Optimizing cells in module \pin_wishbone_0__sel.
  Optimizing cells in module \pin_wishbone_0__stb.
  Optimizing cells in module \pin_wishbone_0__we.
  Optimizing cells in module \pll.
  Optimizing cells in module \postponer.
  Optimizing cells in module \read_antistarvation.
  Optimizing cells in module \refresher.
  Optimizing cells in module \sequencer.
  Optimizing cells in module \steerer.
  Optimizing cells in module \sysclk.
  Optimizing cells in module \tccdcon.
  Optimizing cells in module \tfawcon.
  Optimizing cells in module \timeline.
  Optimizing cells in module \timeline$5.
  Optimizing cells in module \timer.
  Optimizing cells in module \top.
  Optimizing cells in module \trascon.
  Optimizing cells in module \trascon$11.
  Optimizing cells in module \trascon$19.
  Optimizing cells in module \trascon$27.
  Optimizing cells in module \trascon$35.
  Optimizing cells in module \trascon$43.
  Optimizing cells in module \trascon$51.
  Optimizing cells in module \trascon$59.
  Optimizing cells in module \trccon.
  Optimizing cells in module \trccon$10.
  Optimizing cells in module \trccon$18.
  Optimizing cells in module \trccon$26.
  Optimizing cells in module \trccon$34.
  Optimizing cells in module \trccon$42.
  Optimizing cells in module \trccon$50.
  Optimizing cells in module \trccon$58.
  Optimizing cells in module \trrdcon.
  Optimizing cells in module \twtpcon.
  Optimizing cells in module \twtpcon$17.
  Optimizing cells in module \twtpcon$25.
  Optimizing cells in module \twtpcon$33.
  Optimizing cells in module \twtpcon$41.
  Optimizing cells in module \twtpcon$49.
  Optimizing cells in module \twtpcon$57.
  Optimizing cells in module \twtpcon$9.
  Optimizing cells in module \twtrcon.
  Optimizing cells in module \wb_decoder.
  Optimizing cells in module \wb_decoder$4.
  Optimizing cells in module \write_antistarvation.
  Optimizing cells in module \zqcs_executer.
  Optimizing cells in module \zqcs_timer.
Performed a total of 0 changes.

15.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\U$$0'.
Finding identical cells in module `\U$$0$12'.
Finding identical cells in module `\U$$0$20'.
Finding identical cells in module `\U$$0$28'.
Finding identical cells in module `\U$$0$36'.
Finding identical cells in module `\U$$0$44'.
Finding identical cells in module `\U$$0$52'.
Finding identical cells in module `\U$$0$60'.
Finding identical cells in module `\U$$0$64'.
Finding identical cells in module `\U$$1'.
Finding identical cells in module `\U$$1$14'.
Finding identical cells in module `\U$$1$22'.
Finding identical cells in module `\U$$1$30'.
Finding identical cells in module `\U$$1$38'.
Finding identical cells in module `\U$$1$46'.
Finding identical cells in module `\U$$1$54'.
Finding identical cells in module `\U$$1$6'.
Finding identical cells in module `\U$$1$62'.
Finding identical cells in module `\U$$1$65'.
Finding identical cells in module `\U$$2'.
<suppressed ~3 debug messages>
Finding identical cells in module `\U$$2$66'.
Finding identical cells in module `\U$$3'.
Finding identical cells in module `\U$$4'.
Finding identical cells in module `\U$$5'.
Finding identical cells in module `\U$$6'.
Finding identical cells in module `\U$$7'.
Finding identical cells in module `\U$$8'.
Finding identical cells in module `\U$$9'.
Finding identical cells in module `\arbiter'.
Finding identical cells in module `\arbiter$63'.
Finding identical cells in module `\bankmachine0'.
<suppressed ~3 debug messages>
Finding identical cells in module `\bankmachine1'.
<suppressed ~3 debug messages>
Finding identical cells in module `\bankmachine2'.
<suppressed ~3 debug messages>
Finding identical cells in module `\bankmachine3'.
<suppressed ~3 debug messages>
Finding identical cells in module `\bankmachine4'.
<suppressed ~3 debug messages>
Finding identical cells in module `\bankmachine5'.
<suppressed ~3 debug messages>
Finding identical cells in module `\bankmachine6'.
<suppressed ~3 debug messages>
Finding identical cells in module `\bankmachine7'.
<suppressed ~3 debug messages>
Finding identical cells in module `\bridge'.
Finding identical cells in module `\bridge$1'.
Finding identical cells in module `\choose_cmd'.
Finding identical cells in module `\choose_req'.
Finding identical cells in module `\controller'.
Finding identical cells in module `\crossbar'.
Finding identical cells in module `\csr_bridge_0'.
Finding identical cells in module `\csr_bridge_0$3'.
Finding identical cells in module `\csr_mux_0'.
<suppressed ~21 debug messages>
Finding identical cells in module `\csr_mux_0$2'.
Finding identical cells in module `\current_slicer'.
Finding identical cells in module `\current_slicer$16'.
Finding identical cells in module `\current_slicer$24'.
Finding identical cells in module `\current_slicer$32'.
Finding identical cells in module `\current_slicer$40'.
Finding identical cells in module `\current_slicer$48'.
Finding identical cells in module `\current_slicer$56'.
Finding identical cells in module `\current_slicer$8'.
Finding identical cells in module `\ddrphy'.
Finding identical cells in module `\decoder'.
Finding identical cells in module `\dfii'.
Finding identical cells in module `\dqsbufm_manager0'.
Finding identical cells in module `\dqsbufm_manager1'.
Finding identical cells in module `\drambone'.
Finding identical cells in module `\dramcore'.
Finding identical cells in module `\executer'.
Finding identical cells in module `\fifo'.
Finding identical cells in module `\fifo$13'.
Finding identical cells in module `\fifo$21'.
Finding identical cells in module `\fifo$29'.
Finding identical cells in module `\fifo$37'.
Finding identical cells in module `\fifo$45'.
Finding identical cells in module `\fifo$53'.
Finding identical cells in module `\fifo$61'.
Finding identical cells in module `\init'.
Finding identical cells in module `\lookahead_slicer'.
Finding identical cells in module `\lookahead_slicer$15'.
Finding identical cells in module `\lookahead_slicer$23'.
Finding identical cells in module `\lookahead_slicer$31'.
Finding identical cells in module `\lookahead_slicer$39'.
Finding identical cells in module `\lookahead_slicer$47'.
Finding identical cells in module `\lookahead_slicer$55'.
Finding identical cells in module `\lookahead_slicer$7'.
Finding identical cells in module `\multiplexer'.
Finding identical cells in module `\phase_0'.
Finding identical cells in module `\phase_1'.
Finding identical cells in module `\pin_clk100_0'.
Finding identical cells in module `\pin_ddr3_0__a'.
Finding identical cells in module `\pin_ddr3_0__ba'.
Finding identical cells in module `\pin_ddr3_0__cas'.
Finding identical cells in module `\pin_ddr3_0__clk'.
Finding identical cells in module `\pin_ddr3_0__clk_en'.
Finding identical cells in module `\pin_ddr3_0__cs'.
Finding identical cells in module `\pin_ddr3_0__dm'.
Finding identical cells in module `\pin_ddr3_0__odt'.
Finding identical cells in module `\pin_ddr3_0__ras'.
Finding identical cells in module `\pin_ddr3_0__rst'.
Finding identical cells in module `\pin_ddr3_0__we'.
Finding identical cells in module `\pin_rst_0'.
Finding identical cells in module `\pin_wishbone_0__ack'.
Finding identical cells in module `\pin_wishbone_0__adr'.
Finding identical cells in module `\pin_wishbone_0__cyc'.
Finding identical cells in module `\pin_wishbone_0__dat_r'.
Finding identical cells in module `\pin_wishbone_0__dat_w'.
Finding identical cells in module `\pin_wishbone_0__sel'.
Finding identical cells in module `\pin_wishbone_0__stb'.
Finding identical cells in module `\pin_wishbone_0__we'.
Finding identical cells in module `\pll'.
Finding identical cells in module `\postponer'.
Finding identical cells in module `\read_antistarvation'.
<suppressed ~3 debug messages>
Finding identical cells in module `\refresher'.
Finding identical cells in module `\sequencer'.
<suppressed ~6 debug messages>
Finding identical cells in module `\steerer'.
<suppressed ~12 debug messages>
Finding identical cells in module `\sysclk'.
Finding identical cells in module `\tccdcon'.
Finding identical cells in module `\tfawcon'.
Finding identical cells in module `\timeline'.
<suppressed ~15 debug messages>
Finding identical cells in module `\timeline$5'.
<suppressed ~9 debug messages>
Finding identical cells in module `\timer'.
<suppressed ~6 debug messages>
Finding identical cells in module `\top'.
Finding identical cells in module `\trascon'.
Finding identical cells in module `\trascon$11'.
Finding identical cells in module `\trascon$19'.
Finding identical cells in module `\trascon$27'.
Finding identical cells in module `\trascon$35'.
Finding identical cells in module `\trascon$43'.
Finding identical cells in module `\trascon$51'.
Finding identical cells in module `\trascon$59'.
Finding identical cells in module `\trccon'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trccon$10'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trccon$18'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trccon$26'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trccon$34'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trccon$42'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trccon$50'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trccon$58'.
<suppressed ~3 debug messages>
Finding identical cells in module `\trrdcon'.
Finding identical cells in module `\twtpcon'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtpcon$17'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtpcon$25'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtpcon$33'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtpcon$41'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtpcon$49'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtpcon$57'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtpcon$9'.
<suppressed ~3 debug messages>
Finding identical cells in module `\twtrcon'.
<suppressed ~3 debug messages>
Finding identical cells in module `\wb_decoder'.
Finding identical cells in module `\wb_decoder$4'.
Finding identical cells in module `\write_antistarvation'.
<suppressed ~3 debug messages>
Finding identical cells in module `\zqcs_executer'.
Finding identical cells in module `\zqcs_timer'.
<suppressed ~6 debug messages>
Removed a total of 53 cells.

15.13. Executing OPT_DFF pass (perform DFF optimizations).

15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \U$$0..
Finding unused cells or wires in module \U$$0$12..
Finding unused cells or wires in module \U$$0$20..
Finding unused cells or wires in module \U$$0$28..
Finding unused cells or wires in module \U$$0$36..
Finding unused cells or wires in module \U$$0$44..
Finding unused cells or wires in module \U$$0$52..
Finding unused cells or wires in module \U$$0$60..
Finding unused cells or wires in module \U$$0$64..
Finding unused cells or wires in module \U$$1..
Finding unused cells or wires in module \U$$1$14..
Finding unused cells or wires in module \U$$1$22..
Finding unused cells or wires in module \U$$1$30..
Finding unused cells or wires in module \U$$1$38..
Finding unused cells or wires in module \U$$1$46..
Finding unused cells or wires in module \U$$1$54..
Finding unused cells or wires in module \U$$1$6..
Finding unused cells or wires in module \U$$1$62..
Finding unused cells or wires in module \U$$1$65..
Finding unused cells or wires in module \U$$2..
Finding unused cells or wires in module \U$$2$66..
Finding unused cells or wires in module \U$$3..
Finding unused cells or wires in module \U$$4..
Finding unused cells or wires in module \U$$5..
Finding unused cells or wires in module \U$$6..
Finding unused cells or wires in module \U$$7..
Finding unused cells or wires in module \U$$8..
Finding unused cells or wires in module \U$$9..
Finding unused cells or wires in module \arbiter..
Finding unused cells or wires in module \arbiter$63..
Finding unused cells or wires in module \bankmachine0..
Finding unused cells or wires in module \bankmachine1..
Finding unused cells or wires in module \bankmachine2..
Finding unused cells or wires in module \bankmachine3..
Finding unused cells or wires in module \bankmachine4..
Finding unused cells or wires in module \bankmachine5..
Finding unused cells or wires in module \bankmachine6..
Finding unused cells or wires in module \bankmachine7..
Finding unused cells or wires in module \bridge..
Finding unused cells or wires in module \bridge$1..
Finding unused cells or wires in module \choose_cmd..
Finding unused cells or wires in module \choose_req..
Finding unused cells or wires in module \controller..
Finding unused cells or wires in module \crossbar..
Finding unused cells or wires in module \csr_bridge_0..
Finding unused cells or wires in module \csr_bridge_0$3..
Finding unused cells or wires in module \csr_mux_0..
Finding unused cells or wires in module \csr_mux_0$2..
Finding unused cells or wires in module \current_slicer..
Finding unused cells or wires in module \current_slicer$16..
Finding unused cells or wires in module \current_slicer$24..
Finding unused cells or wires in module \current_slicer$32..
Finding unused cells or wires in module \current_slicer$40..
Finding unused cells or wires in module \current_slicer$48..
Finding unused cells or wires in module \current_slicer$56..
Finding unused cells or wires in module \current_slicer$8..
Finding unused cells or wires in module \ddrphy..
Finding unused cells or wires in module \decoder..
Finding unused cells or wires in module \dfii..
Finding unused cells or wires in module \dqsbufm_manager0..
Finding unused cells or wires in module \dqsbufm_manager1..
Finding unused cells or wires in module \drambone..
Finding unused cells or wires in module \dramcore..
Finding unused cells or wires in module \executer..
Finding unused cells or wires in module \fifo..
Finding unused cells or wires in module \fifo$13..
Finding unused cells or wires in module \fifo$21..
Finding unused cells or wires in module \fifo$29..
Finding unused cells or wires in module \fifo$37..
Finding unused cells or wires in module \fifo$45..
Finding unused cells or wires in module \fifo$53..
Finding unused cells or wires in module \fifo$61..
Finding unused cells or wires in module \init..
Finding unused cells or wires in module \lookahead_slicer..
Finding unused cells or wires in module \lookahead_slicer$15..
Finding unused cells or wires in module \lookahead_slicer$23..
Finding unused cells or wires in module \lookahead_slicer$31..
Finding unused cells or wires in module \lookahead_slicer$39..
Finding unused cells or wires in module \lookahead_slicer$47..
Finding unused cells or wires in module \lookahead_slicer$55..
Finding unused cells or wires in module \lookahead_slicer$7..
Finding unused cells or wires in module \multiplexer..
Finding unused cells or wires in module \phase_0..
Finding unused cells or wires in module \phase_1..
Finding unused cells or wires in module \pin_clk100_0..
Finding unused cells or wires in module \pin_ddr3_0__a..
Finding unused cells or wires in module \pin_ddr3_0__ba..
Finding unused cells or wires in module \pin_ddr3_0__cas..
Finding unused cells or wires in module \pin_ddr3_0__clk..
Finding unused cells or wires in module \pin_ddr3_0__clk_en..
Finding unused cells or wires in module \pin_ddr3_0__cs..
Finding unused cells or wires in module \pin_ddr3_0__dm..
Finding unused cells or wires in module \pin_ddr3_0__odt..
Finding unused cells or wires in module \pin_ddr3_0__ras..
Finding unused cells or wires in module \pin_ddr3_0__rst..
Finding unused cells or wires in module \pin_ddr3_0__we..
Finding unused cells or wires in module \pin_rst_0..
Finding unused cells or wires in module \pin_wishbone_0__ack..
Finding unused cells or wires in module \pin_wishbone_0__adr..
Finding unused cells or wires in module \pin_wishbone_0__cyc..
Finding unused cells or wires in module \pin_wishbone_0__dat_r..
Finding unused cells or wires in module \pin_wishbone_0__dat_w..
Finding unused cells or wires in module \pin_wishbone_0__sel..
Finding unused cells or wires in module \pin_wishbone_0__stb..
Finding unused cells or wires in module \pin_wishbone_0__we..
Finding unused cells or wires in module \pll..
Finding unused cells or wires in module \postponer..
Finding unused cells or wires in module \read_antistarvation..
Finding unused cells or wires in module \refresher..
Finding unused cells or wires in module \sequencer..
Finding unused cells or wires in module \steerer..
Finding unused cells or wires in module \sysclk..
Finding unused cells or wires in module \tccdcon..
Finding unused cells or wires in module \tfawcon..
Finding unused cells or wires in module \timeline..
Finding unused cells or wires in module \timeline$5..
Finding unused cells or wires in module \timer..
Finding unused cells or wires in module \top..
Finding unused cells or wires in module \trascon..
Finding unused cells or wires in module \trascon$11..
Finding unused cells or wires in module \trascon$19..
Finding unused cells or wires in module \trascon$27..
Finding unused cells or wires in module \trascon$35..
Finding unused cells or wires in module \trascon$43..
Finding unused cells or wires in module \trascon$51..
Finding unused cells or wires in module \trascon$59..
Finding unused cells or wires in module \trccon..
Finding unused cells or wires in module \trccon$10..
Finding unused cells or wires in module \trccon$18..
Finding unused cells or wires in module \trccon$26..
Finding unused cells or wires in module \trccon$34..
Finding unused cells or wires in module \trccon$42..
Finding unused cells or wires in module \trccon$50..
Finding unused cells or wires in module \trccon$58..
Finding unused cells or wires in module \trrdcon..
Finding unused cells or wires in module \twtpcon..
Finding unused cells or wires in module \twtpcon$17..
Finding unused cells or wires in module \twtpcon$25..
Finding unused cells or wires in module \twtpcon$33..
Finding unused cells or wires in module \twtpcon$41..
Finding unused cells or wires in module \twtpcon$49..
Finding unused cells or wires in module \twtpcon$57..
Finding unused cells or wires in module \twtpcon$9..
Finding unused cells or wires in module \twtrcon..
Finding unused cells or wires in module \wb_decoder..
Finding unused cells or wires in module \wb_decoder$4..
Finding unused cells or wires in module \write_antistarvation..
Finding unused cells or wires in module \zqcs_executer..
Finding unused cells or wires in module \zqcs_timer..
Removed 0 unused cells and 59 unused wires.
<suppressed ~35 debug messages>

15.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module U$$0.
Optimizing module U$$0$12.
Optimizing module U$$0$20.
Optimizing module U$$0$28.
Optimizing module U$$0$36.
Optimizing module U$$0$44.
Optimizing module U$$0$52.
Optimizing module U$$0$60.
Optimizing module U$$0$64.
Optimizing module U$$1.
Optimizing module U$$1$14.
Optimizing module U$$1$22.
Optimizing module U$$1$30.
Optimizing module U$$1$38.
Optimizing module U$$1$46.
Optimizing module U$$1$54.
Optimizing module U$$1$6.
Optimizing module U$$1$62.
Optimizing module U$$1$65.
Optimizing module U$$2.
Optimizing module U$$2$66.
Optimizing module U$$3.
Optimizing module U$$4.
Optimizing module U$$5.
Optimizing module U$$6.
Optimizing module U$$7.
Optimizing module U$$8.
Optimizing module U$$9.
Optimizing module arbiter.
Optimizing module arbiter$63.
Optimizing module bankmachine0.
Optimizing module bankmachine1.
Optimizing module bankmachine2.
Optimizing module bankmachine3.
Optimizing module bankmachine4.
Optimizing module bankmachine5.
Optimizing module bankmachine6.
Optimizing module bankmachine7.
Optimizing module bridge.
Optimizing module bridge$1.
Optimizing module choose_cmd.
Optimizing module choose_req.
Optimizing module controller.
Optimizing module crossbar.
Optimizing module csr_bridge_0.
Optimizing module csr_bridge_0$3.
Optimizing module csr_mux_0.
Optimizing module csr_mux_0$2.
Optimizing module current_slicer.
Optimizing module current_slicer$16.
Optimizing module current_slicer$24.
Optimizing module current_slicer$32.
Optimizing module current_slicer$40.
Optimizing module current_slicer$48.
Optimizing module current_slicer$56.
Optimizing module current_slicer$8.
Optimizing module ddrphy.
Optimizing module decoder.
Optimizing module dfii.
Optimizing module dqsbufm_manager0.
Optimizing module dqsbufm_manager1.
Optimizing module drambone.
Optimizing module dramcore.
Optimizing module executer.
Optimizing module fifo.
Optimizing module fifo$13.
Optimizing module fifo$21.
Optimizing module fifo$29.
Optimizing module fifo$37.
Optimizing module fifo$45.
Optimizing module fifo$53.
Optimizing module fifo$61.
Optimizing module init.
Optimizing module lookahead_slicer.
Optimizing module lookahead_slicer$15.
Optimizing module lookahead_slicer$23.
Optimizing module lookahead_slicer$31.
Optimizing module lookahead_slicer$39.
Optimizing module lookahead_slicer$47.
Optimizing module lookahead_slicer$55.
Optimizing module lookahead_slicer$7.
Optimizing module multiplexer.
Optimizing module phase_0.
Optimizing module phase_1.
Optimizing module pin_clk100_0.
Optimizing module pin_ddr3_0__a.
Optimizing module pin_ddr3_0__ba.
Optimizing module pin_ddr3_0__cas.
Optimizing module pin_ddr3_0__clk.
Optimizing module pin_ddr3_0__clk_en.
Optimizing module pin_ddr3_0__cs.
Optimizing module pin_ddr3_0__dm.
Optimizing module pin_ddr3_0__odt.
Optimizing module pin_ddr3_0__ras.
Optimizing module pin_ddr3_0__rst.
Optimizing module pin_ddr3_0__we.
Optimizing module pin_rst_0.
Optimizing module pin_wishbone_0__ack.
Optimizing module pin_wishbone_0__adr.
Optimizing module pin_wishbone_0__cyc.
Optimizing module pin_wishbone_0__dat_r.
Optimizing module pin_wishbone_0__dat_w.
Optimizing module pin_wishbone_0__sel.
Optimizing module pin_wishbone_0__stb.
Optimizing module pin_wishbone_0__we.
Optimizing module pll.
Optimizing module postponer.
Optimizing module read_antistarvation.
Optimizing module refresher.
Optimizing module sequencer.
Optimizing module steerer.
Optimizing module sysclk.
Optimizing module tccdcon.
Optimizing module tfawcon.
Optimizing module timeline.
Optimizing module timeline$5.
Optimizing module timer.
Optimizing module top.
Optimizing module trascon.
Optimizing module trascon$11.
Optimizing module trascon$19.
Optimizing module trascon$27.
Optimizing module trascon$35.
Optimizing module trascon$43.
Optimizing module trascon$51.
Optimizing module trascon$59.
Optimizing module trccon.
Optimizing module trccon$10.
Optimizing module trccon$18.
Optimizing module trccon$26.
Optimizing module trccon$34.
Optimizing module trccon$42.
Optimizing module trccon$50.
Optimizing module trccon$58.
Optimizing module trrdcon.
Optimizing module twtpcon.
Optimizing module twtpcon$17.
Optimizing module twtpcon$25.
Optimizing module twtpcon$33.
Optimizing module twtpcon$41.
Optimizing module twtpcon$49.
Optimizing module twtpcon$57.
Optimizing module twtpcon$9.
Optimizing module twtrcon.
Optimizing module wb_decoder.
Optimizing module wb_decoder$4.
Optimizing module write_antistarvation.
Optimizing module zqcs_executer.
Optimizing module zqcs_timer.

15.16. Rerunning OPT passes. (Maybe there is more to do..)

15.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \U$$0..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$12..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$20..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$28..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$36..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$44..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$52..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$60..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$0$64..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$14..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$22..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$30..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$38..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$46..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$54..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$6..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$62..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$1$65..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$2..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \U$$2$66..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$3..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$5..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$6..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$7..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$8..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \U$$9..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \arbiter..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \arbiter$63..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine0..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine1..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine2..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine4..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine5..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine6..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bankmachine7..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \bridge..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \bridge$1..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \choose_cmd..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \choose_req..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \controller..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \crossbar..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \csr_bridge_0..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \csr_bridge_0$3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \csr_mux_0..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \csr_mux_0$2..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \current_slicer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$16..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$24..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$32..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$40..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$48..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$56..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \current_slicer$8..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \ddrphy..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \decoder..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \dfii..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \dqsbufm_manager0..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \dqsbufm_manager1..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \drambone..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \dramcore..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \executer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \fifo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$13..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$21..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$29..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$37..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$45..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$53..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \fifo$61..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \init..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$15..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$23..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$31..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$39..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$47..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$55..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \lookahead_slicer$7..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \multiplexer..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \phase_0..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \phase_1..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \pin_clk100_0..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__a..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__ba..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__cas..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__clk..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__clk_en..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__cs..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__dm..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__odt..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__ras..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__rst..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_ddr3_0__we..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_rst_0..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__ack..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__adr..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__cyc..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__dat_r..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__dat_w..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__sel..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__stb..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pin_wishbone_0__we..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \pll..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \postponer..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \read_antistarvation..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \refresher..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \sequencer..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \steerer..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \sysclk..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \tccdcon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \tfawcon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \timeline..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \timeline$5..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \timer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \trascon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$11..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$19..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$27..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$35..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$43..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$51..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trascon$59..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$10..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$18..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$26..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$34..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$42..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$50..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trccon$58..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \trrdcon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$17..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$25..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$33..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$41..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$49..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$57..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtpcon$9..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \twtrcon..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \wb_decoder..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \wb_decoder$4..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \write_antistarvation..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \zqcs_executer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \zqcs_timer..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.
<suppressed ~415 debug messages>

15.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \U$$0.
  Optimizing cells in module \U$$0$12.
  Optimizing cells in module \U$$0$20.
  Optimizing cells in module \U$$0$28.
  Optimizing cells in module \U$$0$36.
  Optimizing cells in module \U$$0$44.
  Optimizing cells in module \U$$0$52.
  Optimizing cells in module \U$$0$60.
  Optimizing cells in module \U$$0$64.
  Optimizing cells in module \U$$1.
  Optimizing cells in module \U$$1$14.
  Optimizing cells in module \U$$1$22.
  Optimizing cells in module \U$$1$30.
  Optimizing cells in module \U$$1$38.
  Optimizing cells in module \U$$1$46.
  Optimizing cells in module \U$$1$54.
  Optimizing cells in module \U$$1$6.
  Optimizing cells in module \U$$1$62.
  Optimizing cells in module \U$$1$65.
  Optimizing cells in module \U$$2.
  Optimizing cells in module \U$$2$66.
  Optimizing cells in module \U$$3.
  Optimizing cells in module \U$$4.
  Optimizing cells in module \U$$5.
  Optimizing cells in module \U$$6.
  Optimizing cells in module \U$$7.
  Optimizing cells in module \U$$8.
  Optimizing cells in module \U$$9.
  Optimizing cells in module \arbiter.
  Optimizing cells in module \arbiter$63.
  Optimizing cells in module \bankmachine0.
  Optimizing cells in module \bankmachine1.
  Optimizing cells in module \bankmachine2.
  Optimizing cells in module \bankmachine3.
  Optimizing cells in module \bankmachine4.
  Optimizing cells in module \bankmachine5.
  Optimizing cells in module \bankmachine6.
  Optimizing cells in module \bankmachine7.
  Optimizing cells in module \bridge.
  Optimizing cells in module \bridge$1.
  Optimizing cells in module \choose_cmd.
  Optimizing cells in module \choose_req.
  Optimizing cells in module \controller.
  Optimizing cells in module \crossbar.
  Optimizing cells in module \csr_bridge_0.
  Optimizing cells in module \csr_bridge_0$3.
  Optimizing cells in module \csr_mux_0.
  Optimizing cells in module \csr_mux_0$2.
  Optimizing cells in module \current_slicer.
  Optimizing cells in module \current_slicer$16.
  Optimizing cells in module \current_slicer$24.
  Optimizing cells in module \current_slicer$32.
  Optimizing cells in module \current_slicer$40.
  Optimizing cells in module \current_slicer$48.
  Optimizing cells in module \current_slicer$56.
  Optimizing cells in module \current_slicer$8.
  Optimizing cells in module \ddrphy.
  Optimizing cells in module \decoder.
  Optimizing cells in module \dfii.
  Optimizing cells in module \dqsbufm_manager0.
  Optimizing cells in module \dqsbufm_manager1.
  Optimizing cells in module \drambone.
  Optimizing cells in module \dramcore.
  Optimizing cells in module \executer.
  Optimizing cells in module \fifo.
  Optimizing cells in module \fifo$13.
  Optimizing cells in module \fifo$21.
  Optimizing cells in module \fifo$29.
  Optimizing cells in module \fifo$37.
  Optimizing cells in module \fifo$45.
  Optimizing cells in module \fifo$53.
  Optimizing cells in module \fifo$61.
  Optimizing cells in module \init.
  Optimizing cells in module \lookahead_slicer.
  Optimizing cells in module \lookahead_slicer$15.
  Optimizing cells in module \lookahead_slicer$23.
  Optimizing cells in module \lookahead_slicer$31.
  Optimizing cells in module \lookahead_slicer$39.
  Optimizing cells in module \lookahead_slicer$47.
  Optimizing cells in module \lookahead_slicer$55.
  Optimizing cells in module \lookahead_slicer$7.
  Optimizing cells in module \multiplexer.
  Optimizing cells in module \phase_0.
  Optimizing cells in module \phase_1.
  Optimizing cells in module \pin_clk100_0.
  Optimizing cells in module \pin_ddr3_0__a.
  Optimizing cells in module \pin_ddr3_0__ba.
  Optimizing cells in module \pin_ddr3_0__cas.
  Optimizing cells in module \pin_ddr3_0__clk.
  Optimizing cells in module \pin_ddr3_0__clk_en.
  Optimizing cells in module \pin_ddr3_0__cs.
  Optimizing cells in module \pin_ddr3_0__dm.
  Optimizing cells in module \pin_ddr3_0__odt.
  Optimizing cells in module \pin_ddr3_0__ras.
  Optimizing cells in module \pin_ddr3_0__rst.
  Optimizing cells in module \pin_ddr3_0__we.
  Optimizing cells in module \pin_rst_0.
  Optimizing cells in module \pin_wishbone_0__ack.
  Optimizing cells in module \pin_wishbone_0__adr.
  Optimizing cells in module \pin_wishbone_0__cyc.
  Optimizing cells in module \pin_wishbone_0__dat_r.
  Optimizing cells in module \pin_wishbone_0__dat_w.
  Optimizing cells in module \pin_wishbone_0__sel.
  Optimizing cells in module \pin_wishbone_0__stb.
  Optimizing cells in module \pin_wishbone_0__we.
  Optimizing cells in module \pll.
  Optimizing cells in module \postponer.
  Optimizing cells in module \read_antistarvation.
  Optimizing cells in module \refresher.
  Optimizing cells in module \sequencer.
  Optimizing cells in module \steerer.
  Optimizing cells in module \sysclk.
  Optimizing cells in module \tccdcon.
  Optimizing cells in module \tfawcon.
  Optimizing cells in module \timeline.
  Optimizing cells in module \timeline$5.
  Optimizing cells in module \timer.
  Optimizing cells in module \top.
  Optimizing cells in module \trascon.
  Optimizing cells in module \trascon$11.
  Optimizing cells in module \trascon$19.
  Optimizing cells in module \trascon$27.
  Optimizing cells in module \trascon$35.
  Optimizing cells in module \trascon$43.
  Optimizing cells in module \trascon$51.
  Optimizing cells in module \trascon$59.
  Optimizing cells in module \trccon.
  Optimizing cells in module \trccon$10.
  Optimizing cells in module \trccon$18.
  Optimizing cells in module \trccon$26.
  Optimizing cells in module \trccon$34.
  Optimizing cells in module \trccon$42.
  Optimizing cells in module \trccon$50.
  Optimizing cells in module \trccon$58.
  Optimizing cells in module \trrdcon.
  Optimizing cells in module \twtpcon.
  Optimizing cells in module \twtpcon$17.
  Optimizing cells in module \twtpcon$25.
  Optimizing cells in module \twtpcon$33.
  Optimizing cells in module \twtpcon$41.
  Optimizing cells in module \twtpcon$49.
  Optimizing cells in module \twtpcon$57.
  Optimizing cells in module \twtpcon$9.
  Optimizing cells in module \twtrcon.
  Optimizing cells in module \wb_decoder.
  Optimizing cells in module \wb_decoder$4.
  Optimizing cells in module \write_antistarvation.
  Optimizing cells in module \zqcs_executer.
  Optimizing cells in module \zqcs_timer.
Performed a total of 0 changes.

15.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\U$$0'.
Finding identical cells in module `\U$$0$12'.
Finding identical cells in module `\U$$0$20'.
Finding identical cells in module `\U$$0$28'.
Finding identical cells in module `\U$$0$36'.
Finding identical cells in module `\U$$0$44'.
Finding identical cells in module `\U$$0$52'.
Finding identical cells in module `\U$$0$60'.
Finding identical cells in module `\U$$0$64'.
Finding identical cells in module `\U$$1'.
Finding identical cells in module `\U$$1$14'.
Finding identical cells in module `\U$$1$22'.
Finding identical cells in module `\U$$1$30'.
Finding identical cells in module `\U$$1$38'.
Finding identical cells in module `\U$$1$46'.
Finding identical cells in module `\U$$1$54'.
Finding identical cells in module `\U$$1$6'.
Finding identical cells in module `\U$$1$62'.
Finding identical cells in module `\U$$1$65'.
Finding identical cells in module `\U$$2'.
Finding identical cells in module `\U$$2$66'.
Finding identical cells in module `\U$$3'.
Finding identical cells in module `\U$$4'.
Finding identical cells in module `\U$$5'.
Finding identical cells in module `\U$$6'.
Finding identical cells in module `\U$$7'.
Finding identical cells in module `\U$$8'.
Finding identical cells in module `\U$$9'.
Finding identical cells in module `\arbiter'.
Finding identical cells in module `\arbiter$63'.
Finding identical cells in module `\bankmachine0'.
Finding identical cells in module `\bankmachine1'.
Finding identical cells in module `\bankmachine2'.
Finding identical cells in module `\bankmachine3'.
Finding identical cells in module `\bankmachine4'.
Finding identical cells in module `\bankmachine5'.
Finding identical cells in module `\bankmachine6'.
Finding identical cells in module `\bankmachine7'.
Finding identical cells in module `\bridge'.
Finding identical cells in module `\bridge$1'.
Finding identical cells in module `\choose_cmd'.
Finding identical cells in module `\choose_req'.
Finding identical cells in module `\controller'.
Finding identical cells in module `\crossbar'.
Finding identical cells in module `\csr_bridge_0'.
Finding identical cells in module `\csr_bridge_0$3'.
Finding identical cells in module `\csr_mux_0'.
Finding identical cells in module `\csr_mux_0$2'.
Finding identical cells in module `\current_slicer'.
Finding identical cells in module `\current_slicer$16'.
Finding identical cells in module `\current_slicer$24'.
Finding identical cells in module `\current_slicer$32'.
Finding identical cells in module `\current_slicer$40'.
Finding identical cells in module `\current_slicer$48'.
Finding identical cells in module `\current_slicer$56'.
Finding identical cells in module `\current_slicer$8'.
Finding identical cells in module `\ddrphy'.
Finding identical cells in module `\decoder'.
Finding identical cells in module `\dfii'.
Finding identical cells in module `\dqsbufm_manager0'.
Finding identical cells in module `\dqsbufm_manager1'.
Finding identical cells in module `\drambone'.
Finding identical cells in module `\dramcore'.
Finding identical cells in module `\executer'.
Finding identical cells in module `\fifo'.
Finding identical cells in module `\fifo$13'.
Finding identical cells in module `\fifo$21'.
Finding identical cells in module `\fifo$29'.
Finding identical cells in module `\fifo$37'.
Finding identical cells in module `\fifo$45'.
Finding identical cells in module `\fifo$53'.
Finding identical cells in module `\fifo$61'.
Finding identical cells in module `\init'.
Finding identical cells in module `\lookahead_slicer'.
Finding identical cells in module `\lookahead_slicer$15'.
Finding identical cells in module `\lookahead_slicer$23'.
Finding identical cells in module `\lookahead_slicer$31'.
Finding identical cells in module `\lookahead_slicer$39'.
Finding identical cells in module `\lookahead_slicer$47'.
Finding identical cells in module `\lookahead_slicer$55'.
Finding identical cells in module `\lookahead_slicer$7'.
Finding identical cells in module `\multiplexer'.
Finding identical cells in module `\phase_0'.
Finding identical cells in module `\phase_1'.
Finding identical cells in module `\pin_clk100_0'.
Finding identical cells in module `\pin_ddr3_0__a'.
Finding identical cells in module `\pin_ddr3_0__ba'.
Finding identical cells in module `\pin_ddr3_0__cas'.
Finding identical cells in module `\pin_ddr3_0__clk'.
Finding identical cells in module `\pin_ddr3_0__clk_en'.
Finding identical cells in module `\pin_ddr3_0__cs'.
Finding identical cells in module `\pin_ddr3_0__dm'.
Finding identical cells in module `\pin_ddr3_0__odt'.
Finding identical cells in module `\pin_ddr3_0__ras'.
Finding identical cells in module `\pin_ddr3_0__rst'.
Finding identical cells in module `\pin_ddr3_0__we'.
Finding identical cells in module `\pin_rst_0'.
Finding identical cells in module `\pin_wishbone_0__ack'.
Finding identical cells in module `\pin_wishbone_0__adr'.
Finding identical cells in module `\pin_wishbone_0__cyc'.
Finding identical cells in module `\pin_wishbone_0__dat_r'.
Finding identical cells in module `\pin_wishbone_0__dat_w'.
Finding identical cells in module `\pin_wishbone_0__sel'.
Finding identical cells in module `\pin_wishbone_0__stb'.
Finding identical cells in module `\pin_wishbone_0__we'.
Finding identical cells in module `\pll'.
Finding identical cells in module `\postponer'.
Finding identical cells in module `\read_antistarvation'.
Finding identical cells in module `\refresher'.
Finding identical cells in module `\sequencer'.
Finding identical cells in module `\steerer'.
Finding identical cells in module `\sysclk'.
Finding identical cells in module `\tccdcon'.
Finding identical cells in module `\tfawcon'.
Finding identical cells in module `\timeline'.
Finding identical cells in module `\timeline$5'.
Finding identical cells in module `\timer'.
Finding identical cells in module `\top'.
Finding identical cells in module `\trascon'.
Finding identical cells in module `\trascon$11'.
Finding identical cells in module `\trascon$19'.
Finding identical cells in module `\trascon$27'.
Finding identical cells in module `\trascon$35'.
Finding identical cells in module `\trascon$43'.
Finding identical cells in module `\trascon$51'.
Finding identical cells in module `\trascon$59'.
Finding identical cells in module `\trccon'.
Finding identical cells in module `\trccon$10'.
Finding identical cells in module `\trccon$18'.
Finding identical cells in module `\trccon$26'.
Finding identical cells in module `\trccon$34'.
Finding identical cells in module `\trccon$42'.
Finding identical cells in module `\trccon$50'.
Finding identical cells in module `\trccon$58'.
Finding identical cells in module `\trrdcon'.
Finding identical cells in module `\twtpcon'.
Finding identical cells in module `\twtpcon$17'.
Finding identical cells in module `\twtpcon$25'.
Finding identical cells in module `\twtpcon$33'.
Finding identical cells in module `\twtpcon$41'.
Finding identical cells in module `\twtpcon$49'.
Finding identical cells in module `\twtpcon$57'.
Finding identical cells in module `\twtpcon$9'.
Finding identical cells in module `\twtrcon'.
Finding identical cells in module `\wb_decoder'.
Finding identical cells in module `\wb_decoder$4'.
Finding identical cells in module `\write_antistarvation'.
Finding identical cells in module `\zqcs_executer'.
Finding identical cells in module `\zqcs_timer'.
Removed a total of 0 cells.

15.20. Executing OPT_DFF pass (perform DFF optimizations).

15.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \U$$0..
Finding unused cells or wires in module \U$$0$12..
Finding unused cells or wires in module \U$$0$20..
Finding unused cells or wires in module \U$$0$28..
Finding unused cells or wires in module \U$$0$36..
Finding unused cells or wires in module \U$$0$44..
Finding unused cells or wires in module \U$$0$52..
Finding unused cells or wires in module \U$$0$60..
Finding unused cells or wires in module \U$$0$64..
Finding unused cells or wires in module \U$$1..
Finding unused cells or wires in module \U$$1$14..
Finding unused cells or wires in module \U$$1$22..
Finding unused cells or wires in module \U$$1$30..
Finding unused cells or wires in module \U$$1$38..
Finding unused cells or wires in module \U$$1$46..
Finding unused cells or wires in module \U$$1$54..
Finding unused cells or wires in module \U$$1$6..
Finding unused cells or wires in module \U$$1$62..
Finding unused cells or wires in module \U$$1$65..
Finding unused cells or wires in module \U$$2..
Finding unused cells or wires in module \U$$2$66..
Finding unused cells or wires in module \U$$3..
Finding unused cells or wires in module \U$$4..
Finding unused cells or wires in module \U$$5..
Finding unused cells or wires in module \U$$6..
Finding unused cells or wires in module \U$$7..
Finding unused cells or wires in module \U$$8..
Finding unused cells or wires in module \U$$9..
Finding unused cells or wires in module \arbiter..
Finding unused cells or wires in module \arbiter$63..
Finding unused cells or wires in module \bankmachine0..
Finding unused cells or wires in module \bankmachine1..
Finding unused cells or wires in module \bankmachine2..
Finding unused cells or wires in module \bankmachine3..
Finding unused cells or wires in module \bankmachine4..
Finding unused cells or wires in module \bankmachine5..
Finding unused cells or wires in module \bankmachine6..
Finding unused cells or wires in module \bankmachine7..
Finding unused cells or wires in module \bridge..
Finding unused cells or wires in module \bridge$1..
Finding unused cells or wires in module \choose_cmd..
Finding unused cells or wires in module \choose_req..
Finding unused cells or wires in module \controller..
Finding unused cells or wires in module \crossbar..
Finding unused cells or wires in module \csr_bridge_0..
Finding unused cells or wires in module \csr_bridge_0$3..
Finding unused cells or wires in module \csr_mux_0..
Finding unused cells or wires in module \csr_mux_0$2..
Finding unused cells or wires in module \current_slicer..
Finding unused cells or wires in module \current_slicer$16..
Finding unused cells or wires in module \current_slicer$24..
Finding unused cells or wires in module \current_slicer$32..
Finding unused cells or wires in module \current_slicer$40..
Finding unused cells or wires in module \current_slicer$48..
Finding unused cells or wires in module \current_slicer$56..
Finding unused cells or wires in module \current_slicer$8..
Finding unused cells or wires in module \ddrphy..
Finding unused cells or wires in module \decoder..
Finding unused cells or wires in module \dfii..
Finding unused cells or wires in module \dqsbufm_manager0..
Finding unused cells or wires in module \dqsbufm_manager1..
Finding unused cells or wires in module \drambone..
Finding unused cells or wires in module \dramcore..
Finding unused cells or wires in module \executer..
Finding unused cells or wires in module \fifo..
Finding unused cells or wires in module \fifo$13..
Finding unused cells or wires in module \fifo$21..
Finding unused cells or wires in module \fifo$29..
Finding unused cells or wires in module \fifo$37..
Finding unused cells or wires in module \fifo$45..
Finding unused cells or wires in module \fifo$53..
Finding unused cells or wires in module \fifo$61..
Finding unused cells or wires in module \init..
Finding unused cells or wires in module \lookahead_slicer..
Finding unused cells or wires in module \lookahead_slicer$15..
Finding unused cells or wires in module \lookahead_slicer$23..
Finding unused cells or wires in module \lookahead_slicer$31..
Finding unused cells or wires in module \lookahead_slicer$39..
Finding unused cells or wires in module \lookahead_slicer$47..
Finding unused cells or wires in module \lookahead_slicer$55..
Finding unused cells or wires in module \lookahead_slicer$7..
Finding unused cells or wires in module \multiplexer..
Finding unused cells or wires in module \phase_0..
Finding unused cells or wires in module \phase_1..
Finding unused cells or wires in module \pin_clk100_0..
Finding unused cells or wires in module \pin_ddr3_0__a..
Finding unused cells or wires in module \pin_ddr3_0__ba..
Finding unused cells or wires in module \pin_ddr3_0__cas..
Finding unused cells or wires in module \pin_ddr3_0__clk..
Finding unused cells or wires in module \pin_ddr3_0__clk_en..
Finding unused cells or wires in module \pin_ddr3_0__cs..
Finding unused cells or wires in module \pin_ddr3_0__dm..
Finding unused cells or wires in module \pin_ddr3_0__odt..
Finding unused cells or wires in module \pin_ddr3_0__ras..
Finding unused cells or wires in module \pin_ddr3_0__rst..
Finding unused cells or wires in module \pin_ddr3_0__we..
Finding unused cells or wires in module \pin_rst_0..
Finding unused cells or wires in module \pin_wishbone_0__ack..
Finding unused cells or wires in module \pin_wishbone_0__adr..
Finding unused cells or wires in module \pin_wishbone_0__cyc..
Finding unused cells or wires in module \pin_wishbone_0__dat_r..
Finding unused cells or wires in module \pin_wishbone_0__dat_w..
Finding unused cells or wires in module \pin_wishbone_0__sel..
Finding unused cells or wires in module \pin_wishbone_0__stb..
Finding unused cells or wires in module \pin_wishbone_0__we..
Finding unused cells or wires in module \pll..
Finding unused cells or wires in module \postponer..
Finding unused cells or wires in module \read_antistarvation..
Finding unused cells or wires in module \refresher..
Finding unused cells or wires in module \sequencer..
Finding unused cells or wires in module \steerer..
Finding unused cells or wires in module \sysclk..
Finding unused cells or wires in module \tccdcon..
Finding unused cells or wires in module \tfawcon..
Finding unused cells or wires in module \timeline..
Finding unused cells or wires in module \timeline$5..
Finding unused cells or wires in module \timer..
Finding unused cells or wires in module \top..
Finding unused cells or wires in module \trascon..
Finding unused cells or wires in module \trascon$11..
Finding unused cells or wires in module \trascon$19..
Finding unused cells or wires in module \trascon$27..
Finding unused cells or wires in module \trascon$35..
Finding unused cells or wires in module \trascon$43..
Finding unused cells or wires in module \trascon$51..
Finding unused cells or wires in module \trascon$59..
Finding unused cells or wires in module \trccon..
Finding unused cells or wires in module \trccon$10..
Finding unused cells or wires in module \trccon$18..
Finding unused cells or wires in module \trccon$26..
Finding unused cells or wires in module \trccon$34..
Finding unused cells or wires in module \trccon$42..
Finding unused cells or wires in module \trccon$50..
Finding unused cells or wires in module \trccon$58..
Finding unused cells or wires in module \trrdcon..
Finding unused cells or wires in module \twtpcon..
Finding unused cells or wires in module \twtpcon$17..
Finding unused cells or wires in module \twtpcon$25..
Finding unused cells or wires in module \twtpcon$33..
Finding unused cells or wires in module \twtpcon$41..
Finding unused cells or wires in module \twtpcon$49..
Finding unused cells or wires in module \twtpcon$57..
Finding unused cells or wires in module \twtpcon$9..
Finding unused cells or wires in module \twtrcon..
Finding unused cells or wires in module \wb_decoder..
Finding unused cells or wires in module \wb_decoder$4..
Finding unused cells or wires in module \write_antistarvation..
Finding unused cells or wires in module \zqcs_executer..
Finding unused cells or wires in module \zqcs_timer..

15.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module U$$0.
Optimizing module U$$0$12.
Optimizing module U$$0$20.
Optimizing module U$$0$28.
Optimizing module U$$0$36.
Optimizing module U$$0$44.
Optimizing module U$$0$52.
Optimizing module U$$0$60.
Optimizing module U$$0$64.
Optimizing module U$$1.
Optimizing module U$$1$14.
Optimizing module U$$1$22.
Optimizing module U$$1$30.
Optimizing module U$$1$38.
Optimizing module U$$1$46.
Optimizing module U$$1$54.
Optimizing module U$$1$6.
Optimizing module U$$1$62.
Optimizing module U$$1$65.
Optimizing module U$$2.
Optimizing module U$$2$66.
Optimizing module U$$3.
Optimizing module U$$4.
Optimizing module U$$5.
Optimizing module U$$6.
Optimizing module U$$7.
Optimizing module U$$8.
Optimizing module U$$9.
Optimizing module arbiter.
Optimizing module arbiter$63.
Optimizing module bankmachine0.
Optimizing module bankmachine1.
Optimizing module bankmachine2.
Optimizing module bankmachine3.
Optimizing module bankmachine4.
Optimizing module bankmachine5.
Optimizing module bankmachine6.
Optimizing module bankmachine7.
Optimizing module bridge.
Optimizing module bridge$1.
Optimizing module choose_cmd.
Optimizing module choose_req.
Optimizing module controller.
Optimizing module crossbar.
Optimizing module csr_bridge_0.
Optimizing module csr_bridge_0$3.
Optimizing module csr_mux_0.
Optimizing module csr_mux_0$2.
Optimizing module current_slicer.
Optimizing module current_slicer$16.
Optimizing module current_slicer$24.
Optimizing module current_slicer$32.
Optimizing module current_slicer$40.
Optimizing module current_slicer$48.
Optimizing module current_slicer$56.
Optimizing module current_slicer$8.
Optimizing module ddrphy.
Optimizing module decoder.
Optimizing module dfii.
Optimizing module dqsbufm_manager0.
Optimizing module dqsbufm_manager1.
Optimizing module drambone.
Optimizing module dramcore.
Optimizing module executer.
Optimizing module fifo.
Optimizing module fifo$13.
Optimizing module fifo$21.
Optimizing module fifo$29.
Optimizing module fifo$37.
Optimizing module fifo$45.
Optimizing module fifo$53.
Optimizing module fifo$61.
Optimizing module init.
Optimizing module lookahead_slicer.
Optimizing module lookahead_slicer$15.
Optimizing module lookahead_slicer$23.
Optimizing module lookahead_slicer$31.
Optimizing module lookahead_slicer$39.
Optimizing module lookahead_slicer$47.
Optimizing module lookahead_slicer$55.
Optimizing module lookahead_slicer$7.
Optimizing module multiplexer.
Optimizing module phase_0.
Optimizing module phase_1.
Optimizing module pin_clk100_0.
Optimizing module pin_ddr3_0__a.
Optimizing module pin_ddr3_0__ba.
Optimizing module pin_ddr3_0__cas.
Optimizing module pin_ddr3_0__clk.
Optimizing module pin_ddr3_0__clk_en.
Optimizing module pin_ddr3_0__cs.
Optimizing module pin_ddr3_0__dm.
Optimizing module pin_ddr3_0__odt.
Optimizing module pin_ddr3_0__ras.
Optimizing module pin_ddr3_0__rst.
Optimizing module pin_ddr3_0__we.
Optimizing module pin_rst_0.
Optimizing module pin_wishbone_0__ack.
Optimizing module pin_wishbone_0__adr.
Optimizing module pin_wishbone_0__cyc.
Optimizing module pin_wishbone_0__dat_r.
Optimizing module pin_wishbone_0__dat_w.
Optimizing module pin_wishbone_0__sel.
Optimizing module pin_wishbone_0__stb.
Optimizing module pin_wishbone_0__we.
Optimizing module pll.
Optimizing module postponer.
Optimizing module read_antistarvation.
Optimizing module refresher.
Optimizing module sequencer.
Optimizing module steerer.
Optimizing module sysclk.
Optimizing module tccdcon.
Optimizing module tfawcon.
Optimizing module timeline.
Optimizing module timeline$5.
Optimizing module timer.
Optimizing module top.
Optimizing module trascon.
Optimizing module trascon$11.
Optimizing module trascon$19.
Optimizing module trascon$27.
Optimizing module trascon$35.
Optimizing module trascon$43.
Optimizing module trascon$51.
Optimizing module trascon$59.
Optimizing module trccon.
Optimizing module trccon$10.
Optimizing module trccon$18.
Optimizing module trccon$26.
Optimizing module trccon$34.
Optimizing module trccon$42.
Optimizing module trccon$50.
Optimizing module trccon$58.
Optimizing module trrdcon.
Optimizing module twtpcon.
Optimizing module twtpcon$17.
Optimizing module twtpcon$25.
Optimizing module twtpcon$33.
Optimizing module twtpcon$41.
Optimizing module twtpcon$49.
Optimizing module twtpcon$57.
Optimizing module twtpcon$9.
Optimizing module twtrcon.
Optimizing module wb_decoder.
Optimizing module wb_decoder$4.
Optimizing module write_antistarvation.
Optimizing module zqcs_executer.
Optimizing module zqcs_timer.

15.23. Finished OPT passes. (There is nothing left to do.)

16. Executing Verilog backend.
Dumping module `\U$$0'.
Dumping module `\U$$0$12'.
Dumping module `\U$$0$20'.
Dumping module `\U$$0$28'.
Dumping module `\U$$0$36'.
Dumping module `\U$$0$44'.
Dumping module `\U$$0$52'.
Dumping module `\U$$0$60'.
Dumping module `\U$$0$64'.
Dumping module `\U$$1'.
Dumping module `\U$$1$14'.
Dumping module `\U$$1$22'.
Dumping module `\U$$1$30'.
Dumping module `\U$$1$38'.
Dumping module `\U$$1$46'.
Dumping module `\U$$1$54'.
Dumping module `\U$$1$6'.
Dumping module `\U$$1$62'.
Dumping module `\U$$1$65'.
Dumping module `\U$$2'.
Dumping module `\U$$2$66'.
Dumping module `\U$$3'.
Dumping module `\U$$4'.
Dumping module `\U$$5'.
Dumping module `\U$$6'.
Dumping module `\U$$7'.
Dumping module `\U$$8'.
Dumping module `\U$$9'.
Dumping module `\arbiter'.
Dumping module `\arbiter$63'.
Dumping module `\bankmachine0'.
Dumping module `\bankmachine1'.
Dumping module `\bankmachine2'.
Dumping module `\bankmachine3'.
Dumping module `\bankmachine4'.
Dumping module `\bankmachine5'.
Dumping module `\bankmachine6'.
Dumping module `\bankmachine7'.
Dumping module `\bridge'.
Dumping module `\bridge$1'.
Dumping module `\choose_cmd'.
Dumping module `\choose_req'.
Dumping module `\controller'.
Dumping module `\crossbar'.
Dumping module `\csr_bridge_0'.
Dumping module `\csr_bridge_0$3'.
Dumping module `\csr_mux_0'.
Dumping module `\csr_mux_0$2'.
Dumping module `\current_slicer'.
Dumping module `\current_slicer$16'.
Dumping module `\current_slicer$24'.
Dumping module `\current_slicer$32'.
Dumping module `\current_slicer$40'.
Dumping module `\current_slicer$48'.
Dumping module `\current_slicer$56'.
Dumping module `\current_slicer$8'.
Dumping module `\ddrphy'.
Dumping module `\decoder'.
Dumping module `\dfii'.
Dumping module `\dqsbufm_manager0'.
Dumping module `\dqsbufm_manager1'.
Dumping module `\drambone'.
Dumping module `\dramcore'.
Dumping module `\executer'.
Dumping module `\fifo'.
Dumping module `\fifo$13'.
Dumping module `\fifo$21'.
Dumping module `\fifo$29'.
Dumping module `\fifo$37'.
Dumping module `\fifo$45'.
Dumping module `\fifo$53'.
Dumping module `\fifo$61'.
Dumping module `\init'.
Dumping module `\lookahead_slicer'.
Dumping module `\lookahead_slicer$15'.
Dumping module `\lookahead_slicer$23'.
Dumping module `\lookahead_slicer$31'.
Dumping module `\lookahead_slicer$39'.
Dumping module `\lookahead_slicer$47'.
Dumping module `\lookahead_slicer$55'.
Dumping module `\lookahead_slicer$7'.
Dumping module `\multiplexer'.
Dumping module `\phase_0'.
Dumping module `\phase_1'.
Dumping module `\pin_clk100_0'.
Dumping module `\pin_ddr3_0__a'.
Dumping module `\pin_ddr3_0__ba'.
Dumping module `\pin_ddr3_0__cas'.
Dumping module `\pin_ddr3_0__clk'.
Dumping module `\pin_ddr3_0__clk_en'.
Dumping module `\pin_ddr3_0__cs'.
Dumping module `\pin_ddr3_0__dm'.
Dumping module `\pin_ddr3_0__odt'.
Dumping module `\pin_ddr3_0__ras'.
Dumping module `\pin_ddr3_0__rst'.
Dumping module `\pin_ddr3_0__we'.
Dumping module `\pin_rst_0'.
Dumping module `\pin_wishbone_0__ack'.
Dumping module `\pin_wishbone_0__adr'.
Dumping module `\pin_wishbone_0__cyc'.
Dumping module `\pin_wishbone_0__dat_r'.
Dumping module `\pin_wishbone_0__dat_w'.
Dumping module `\pin_wishbone_0__sel'.
Dumping module `\pin_wishbone_0__stb'.
Dumping module `\pin_wishbone_0__we'.
Dumping module `\pll'.
Dumping module `\postponer'.
Dumping module `\read_antistarvation'.
Dumping module `\refresher'.
Dumping module `\sequencer'.
Dumping module `\steerer'.
Dumping module `\sysclk'.
Dumping module `\tccdcon'.
Dumping module `\tfawcon'.
Dumping module `\timeline'.
Dumping module `\timeline$5'.
Dumping module `\timer'.
Dumping module `\top'.
Dumping module `\trascon'.
Dumping module `\trascon$11'.
Dumping module `\trascon$19'.
Dumping module `\trascon$27'.
Dumping module `\trascon$35'.
Dumping module `\trascon$43'.
Dumping module `\trascon$51'.
Dumping module `\trascon$59'.
Dumping module `\trccon'.
Dumping module `\trccon$10'.
Dumping module `\trccon$18'.
Dumping module `\trccon$26'.
Dumping module `\trccon$34'.
Dumping module `\trccon$42'.
Dumping module `\trccon$50'.
Dumping module `\trccon$58'.
Dumping module `\trrdcon'.
Dumping module `\twtpcon'.
Dumping module `\twtpcon$17'.
Dumping module `\twtpcon$25'.
Dumping module `\twtpcon$33'.
Dumping module `\twtpcon$41'.
Dumping module `\twtpcon$49'.
Dumping module `\twtpcon$57'.
Dumping module `\twtpcon$9'.
Dumping module `\twtrcon'.
Dumping module `\wb_decoder'.
Dumping module `\wb_decoder$4'.
Dumping module `\write_antistarvation'.
Dumping module `\zqcs_executer'.
Dumping module `\zqcs_timer'.

17. Printing statistics.

=== U$$0 ===

   Number of wires:                 28
   Number of wire bits:            148
   Number of public wires:          28
   Number of public wire bits:     148
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     fifo                            1

=== U$$0$12 ===

   Number of wires:                 28
   Number of wire bits:            148
   Number of public wires:          28
   Number of public wire bits:     148
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     fifo$13                         1

=== U$$0$20 ===

   Number of wires:                 28
   Number of wire bits:            148
   Number of public wires:          28
   Number of public wire bits:     148
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     fifo$21                         1

=== U$$0$28 ===

   Number of wires:                 28
   Number of wire bits:            148
   Number of public wires:          28
   Number of public wire bits:     148
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     fifo$29                         1

=== U$$0$36 ===

   Number of wires:                 28
   Number of wire bits:            148
   Number of public wires:          28
   Number of public wire bits:     148
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     fifo$37                         1

=== U$$0$44 ===

   Number of wires:                 28
   Number of wire bits:            148
   Number of public wires:          28
   Number of public wire bits:     148
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     fifo$45                         1

=== U$$0$52 ===

   Number of wires:                 28
   Number of wire bits:            148
   Number of public wires:          28
   Number of public wire bits:     148
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     fifo$53                         1

=== U$$0$60 ===

   Number of wires:                 28
   Number of wire bits:            148
   Number of public wires:          28
   Number of public wire bits:     148
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     fifo$61                         1

=== U$$0$64 ===

   Number of wires:                  5
   Number of wire bits:             12
   Number of public wires:           5
   Number of public wire bits:      12
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== U$$1 ===

   Number of wires:                  8
   Number of wire bits:              8
   Number of public wires:           8
   Number of public wire bits:       8
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     $dff                            2

=== U$$1$14 ===

   Number of wires:                 13
   Number of wire bits:             51
   Number of public wires:          12
   Number of public wire bits:      50
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  5
     $not                            1
     $or                             1
     $sdffe                          3

=== U$$1$22 ===

   Number of wires:                 13
   Number of wire bits:             51
   Number of public wires:          12
   Number of public wire bits:      50
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  5
     $not                            1
     $or                             1
     $sdffe                          3

=== U$$1$30 ===

   Number of wires:                 13
   Number of wire bits:             51
   Number of public wires:          12
   Number of public wire bits:      50
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  5
     $not                            1
     $or                             1
     $sdffe                          3

=== U$$1$38 ===

   Number of wires:                 13
   Number of wire bits:             51
   Number of public wires:          12
   Number of public wire bits:      50
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  5
     $not                            1
     $or                             1
     $sdffe                          3

=== U$$1$46 ===

   Number of wires:                 13
   Number of wire bits:             51
   Number of public wires:          12
   Number of public wire bits:      50
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  5
     $not                            1
     $or                             1
     $sdffe                          3

=== U$$1$54 ===

   Number of wires:                 13
   Number of wire bits:             51
   Number of public wires:          12
   Number of public wire bits:      50
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  5
     $not                            1
     $or                             1
     $sdffe                          3

=== U$$1$6 ===

   Number of wires:                 13
   Number of wire bits:             51
   Number of public wires:          12
   Number of public wire bits:      50
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  5
     $not                            1
     $or                             1
     $sdffe                          3

=== U$$1$62 ===

   Number of wires:                 13
   Number of wire bits:             51
   Number of public wires:          12
   Number of public wire bits:      50
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  5
     $not                            1
     $or                             1
     $sdffe                          3

=== U$$1$65 ===

   Number of wires:                  5
   Number of wire bits:             12
   Number of public wires:           5
   Number of public wire bits:      12
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== U$$2 ===

   Number of wires:                 21
   Number of wire bits:             46
   Number of public wires:           7
   Number of public wire bits:      13
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 18
     $add                            1
     $eq                             6
     $mux                            2
     $reduce_bool                    2
     $reduce_or                      3
     $sdffe                          4

=== U$$2$66 ===

   Number of wires:                  5
   Number of wire bits:             12
   Number of public wires:           5
   Number of public wire bits:      12
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== U$$3 ===

   Number of wires:                  5
   Number of wire bits:             12
   Number of public wires:           5
   Number of public wire bits:      12
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== U$$4 ===

   Number of wires:                  5
   Number of wire bits:             12
   Number of public wires:           5
   Number of public wire bits:      12
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== U$$5 ===

   Number of wires:                  5
   Number of wire bits:             12
   Number of public wires:           5
   Number of public wire bits:      12
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== U$$6 ===

   Number of wires:                  5
   Number of wire bits:             12
   Number of public wires:           5
   Number of public wire bits:      12
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== U$$7 ===

   Number of wires:                  5
   Number of wire bits:             12
   Number of public wires:           5
   Number of public wire bits:      12
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== U$$8 ===

   Number of wires:                  5
   Number of wire bits:              8
   Number of public wires:           5
   Number of public wire bits:       8
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     $sdff                           1

=== U$$9 ===

   Number of wires:                  5
   Number of wire bits:             18
   Number of public wires:           5
   Number of public wire bits:      18
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     $sdff                           1

=== arbiter ===

   Number of wires:                 93
   Number of wire bits:            230
   Number of public wires:           6
   Number of public wire bits:      15
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 88
     $eq                             7
     $logic_not                      1
     $mux                           64
     $ne                             8
     $not                            1
     $or                             3
     $reduce_and                     1
     $reduce_bool                    1
     $reduce_or                      1
     $sdffe                          1

=== arbiter$63 ===

   Number of wires:                 93
   Number of wire bits:            230
   Number of public wires:           6
   Number of public wire bits:      15
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 88
     $eq                             7
     $logic_not                      1
     $mux                           64
     $ne                             8
     $not                            1
     $or                             3
     $reduce_and                     1
     $reduce_bool                    1
     $reduce_or                      1
     $sdffe                          1

=== bankmachine0 ===

   Number of wires:                154
   Number of wire bits:            407
   Number of public wires:          61
   Number of public wire bits:     255
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                122
     $and                            6
     $eq                             8
     $logic_not                      1
     $mux                           71
     $ne                            11
     $not                            1
     $or                             9
     $reduce_and                     2
     $reduce_bool                    1
     $reduce_or                      2
     $sdffe                          3
     U$$0                            1
     U$$1$6                          1
     current_slicer                  1
     lookahead_slicer                1
     trascon                         1
     trccon                          1
     twtpcon                         1

=== bankmachine1 ===

   Number of wires:                154
   Number of wire bits:            407
   Number of public wires:          61
   Number of public wire bits:     255
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                122
     $and                            6
     $eq                             8
     $logic_not                      1
     $mux                           71
     $ne                            11
     $not                            1
     $or                             9
     $reduce_and                     2
     $reduce_bool                    1
     $reduce_or                      2
     $sdffe                          3
     U$$0$12                         1
     U$$1$14                         1
     current_slicer$8                1
     lookahead_slicer$7              1
     trascon$11                      1
     trccon$10                       1
     twtpcon$9                       1

=== bankmachine2 ===

   Number of wires:                154
   Number of wire bits:            407
   Number of public wires:          61
   Number of public wire bits:     255
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                122
     $and                            6
     $eq                             8
     $logic_not                      1
     $mux                           71
     $ne                            11
     $not                            1
     $or                             9
     $reduce_and                     2
     $reduce_bool                    1
     $reduce_or                      2
     $sdffe                          3
     U$$0$20                         1
     U$$1$22                         1
     current_slicer$16               1
     lookahead_slicer$15             1
     trascon$19                      1
     trccon$18                       1
     twtpcon$17                      1

=== bankmachine3 ===

   Number of wires:                154
   Number of wire bits:            407
   Number of public wires:          61
   Number of public wire bits:     255
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                122
     $and                            6
     $eq                             8
     $logic_not                      1
     $mux                           71
     $ne                            11
     $not                            1
     $or                             9
     $reduce_and                     2
     $reduce_bool                    1
     $reduce_or                      2
     $sdffe                          3
     U$$0$28                         1
     U$$1$30                         1
     current_slicer$24               1
     lookahead_slicer$23             1
     trascon$27                      1
     trccon$26                       1
     twtpcon$25                      1

=== bankmachine4 ===

   Number of wires:                154
   Number of wire bits:            407
   Number of public wires:          61
   Number of public wire bits:     255
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                122
     $and                            6
     $eq                             8
     $logic_not                      1
     $mux                           71
     $ne                            11
     $not                            1
     $or                             9
     $reduce_and                     2
     $reduce_bool                    1
     $reduce_or                      2
     $sdffe                          3
     U$$0$36                         1
     U$$1$38                         1
     current_slicer$32               1
     lookahead_slicer$31             1
     trascon$35                      1
     trccon$34                       1
     twtpcon$33                      1

=== bankmachine5 ===

   Number of wires:                154
   Number of wire bits:            407
   Number of public wires:          61
   Number of public wire bits:     255
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                122
     $and                            6
     $eq                             8
     $logic_not                      1
     $mux                           71
     $ne                            11
     $not                            1
     $or                             9
     $reduce_and                     2
     $reduce_bool                    1
     $reduce_or                      2
     $sdffe                          3
     U$$0$44                         1
     U$$1$46                         1
     current_slicer$40               1
     lookahead_slicer$39             1
     trascon$43                      1
     trccon$42                       1
     twtpcon$41                      1

=== bankmachine6 ===

   Number of wires:                154
   Number of wire bits:            407
   Number of public wires:          61
   Number of public wire bits:     255
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                122
     $and                            6
     $eq                             8
     $logic_not                      1
     $mux                           71
     $ne                            11
     $not                            1
     $or                             9
     $reduce_and                     2
     $reduce_bool                    1
     $reduce_or                      2
     $sdffe                          3
     U$$0$52                         1
     U$$1$54                         1
     current_slicer$48               1
     lookahead_slicer$47             1
     trascon$51                      1
     trccon$50                       1
     twtpcon$49                      1

=== bankmachine7 ===

   Number of wires:                154
   Number of wire bits:            407
   Number of public wires:          61
   Number of public wire bits:     255
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                122
     $and                            6
     $eq                             8
     $logic_not                      1
     $mux                           71
     $ne                            11
     $not                            1
     $or                             9
     $reduce_and                     2
     $reduce_bool                    1
     $reduce_or                      2
     $sdffe                          3
     U$$0$60                         1
     U$$1$62                         1
     current_slicer$56               1
     lookahead_slicer$55             1
     trascon$59                      1
     trccon$58                       1
     twtpcon$57                      1

=== bridge ===

   Number of wires:                 29
   Number of wire bits:            184
   Number of public wires:          29
   Number of public wire bits:     184
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  3
     csr_bridge_0                    1
     csr_mux_0                       1
     wb_decoder                      1

=== bridge$1 ===

   Number of wires:                 36
   Number of wire bits:            488
   Number of public wires:          36
   Number of public wire bits:     488
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  3
     csr_bridge_0$3                  1
     csr_mux_0$2                     1
     wb_decoder$4                    1

=== choose_cmd ===

   Number of wires:                189
   Number of wire bits:            422
   Number of public wires:          91
   Number of public wire bits:     240
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                123
     $and                           25
     $eq                            10
     $logic_not                      1
     $mux                           67
     $not                           16
     $or                             2
     $reduce_or                      1
     arbiter                         1

=== choose_req ===

   Number of wires:                189
   Number of wire bits:            422
   Number of public wires:          91
   Number of public wire bits:     240
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                123
     $and                           25
     $eq                            26
     $logic_not                      1
     $mux                           67
     $or                             2
     $reduce_or                      1
     arbiter$63                      1

=== controller ===

   Number of wires:                249
   Number of wire bits:           1242
   Number of public wires:         249
   Number of public wire bits:    1242
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 10
     bankmachine0                    1
     bankmachine1                    1
     bankmachine2                    1
     bankmachine3                    1
     bankmachine4                    1
     bankmachine5                    1
     bankmachine6                    1
     bankmachine7                    1
     multiplexer                     1
     refresher                       1

=== crossbar ===

   Number of wires:                173
   Number of wire bits:            885
   Number of public wires:          90
   Number of public wire bits:     802
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 98
     $and                           24
     $eq                             7
     $logic_not                      1
     $mux                            2
     $not                            8
     $or                            54
     U$$8                            1
     U$$9                            1

=== csr_bridge_0 ===

   Number of wires:                 62
   Number of wire bits:            183
   Number of public wires:          17
   Number of public wire bits:     102
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 55
     $and                            9
     $eq                             3
     $logic_not                      1
     $mux                           20
     $not                            5
     $or                             2
     $reduce_and                     5
     $reduce_bool                    2
     $reduce_or                      2
     $sdff                           1
     $sdffe                          5

=== csr_bridge_0$3 ===

   Number of wires:                 62
   Number of wire bits:            189
   Number of public wires:          17
   Number of public wire bits:     108
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 55
     $and                            9
     $eq                             3
     $logic_not                      1
     $mux                           20
     $not                            5
     $or                             2
     $reduce_and                     5
     $reduce_bool                    2
     $reduce_or                      2
     $sdff                           1
     $sdffe                          5

=== csr_mux_0 ===

   Number of wires:                 83
   Number of wire bits:            198
   Number of public wires:          26
   Number of public wire bits:      76
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 69
     $eq                            15
     $logic_not                      1
     $mux                           24
     $not                            3
     $or                             7
     $reduce_and                     4
     $reduce_bool                    1
     $reduce_or                      3
     $sdff                           7
     $sdffe                          4

=== csr_mux_0$2 ===

   Number of wires:                159
   Number of wire bits:           1101
   Number of public wires:          33
   Number of public wire bits:     653
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                158
     $eq                            42
     $logic_not                      1
     $mux                           32
     $not                            2
     $or                            19
     $reduce_and                    27
     $reduce_or                      4
     $sdff                           4
     $sdffe                         27

=== current_slicer ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== current_slicer$16 ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== current_slicer$24 ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== current_slicer$32 ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== current_slicer$40 ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== current_slicer$48 ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== current_slicer$56 ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== current_slicer$8 ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== ddrphy ===

   Number of wires:                359
   Number of wire bits:           1381
   Number of public wires:         334
   Number of public wire bits:    1356
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                190
     $and                            7
     $dff                           38
     $mux                           18
     $not                           14
     $or                             6
     $reduce_and                     2
     $sdff                           5
     $sdffe                          6
     BB                             18
     DELAYG                         16
     DQSBUFM                         2
     IDDRX2DQA                      16
     ODDRX2DQA                      18
     ODDRX2DQSB                      2
     TSHX2DQA                       16
     TSHX2DQSA                       2
     bridge                          1
     dqsbufm_manager0                1
     dqsbufm_manager1                1
     init                            1

=== decoder ===

   Number of wires:                 39
   Number of wire bits:            422
   Number of public wires:          32
   Number of public wire bits:     353
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 12
     $eq                             3
     $mux                            6
     $or                             3

=== dfii ===

   Number of wires:                111
   Number of wire bits:           1286
   Number of public wires:         111
   Number of public wire bits:    1286
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 39
     $mux                           36
     $not                            1
     phase_0                         1
     phase_1                         1

=== dqsbufm_manager0 ===

   Number of wires:                 34
   Number of wire bits:             71
   Number of public wires:           7
   Number of public wire bits:      14
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 30
     $eq                             8
     $logic_not                      1
     $mux                           10
     $ne                             1
     $or                             2
     $reduce_and                     2
     $reduce_bool                    1
     $reduce_or                      2
     $sdffe                          3

=== dqsbufm_manager1 ===

   Number of wires:                 34
   Number of wire bits:             71
   Number of public wires:           7
   Number of public wire bits:      14
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 30
     $eq                             8
     $logic_not                      1
     $mux                           10
     $ne                             1
     $or                             2
     $reduce_and                     2
     $reduce_bool                    1
     $reduce_or                      2
     $sdffe                          3

=== drambone ===

   Number of wires:                 59
   Number of wire bits:            995
   Number of public wires:          22
   Number of public wire bits:     407
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 46
     $and                            3
     $eq                             5
     $logic_not                      3
     $mux                           27
     $ne                             3
     $or                             2
     $reduce_and                     1
     $reduce_bool                    1
     $sdffe                          1

=== dramcore ===

   Number of wires:                219
   Number of wire bits:           2470
   Number of public wires:         219
   Number of public wire bits:    2470
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  4
     bridge$1                        1
     controller                      1
     crossbar                        1
     dfii                            1

=== executer ===

   Number of wires:                 10
   Number of wire bits:             24
   Number of public wires:          10
   Number of public wire bits:      24
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     timeline                        1

=== fifo ===

   Number of wires:                 30
   Number of wire bits:            155
   Number of public wires:          18
   Number of public wire bits:     123
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 19
     $add                            3
     $and                            4
     $mem_v2                         1
     $mux                            2
     $ne                             1
     $not                            2
     $reduce_bool                    2
     $sdffe                          3
     $sub                            1

=== fifo$13 ===

   Number of wires:                 30
   Number of wire bits:            155
   Number of public wires:          18
   Number of public wire bits:     123
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 19
     $add                            3
     $and                            4
     $mem_v2                         1
     $mux                            2
     $ne                             1
     $not                            2
     $reduce_bool                    2
     $sdffe                          3
     $sub                            1

=== fifo$21 ===

   Number of wires:                 30
   Number of wire bits:            155
   Number of public wires:          18
   Number of public wire bits:     123
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 19
     $add                            3
     $and                            4
     $mem_v2                         1
     $mux                            2
     $ne                             1
     $not                            2
     $reduce_bool                    2
     $sdffe                          3
     $sub                            1

=== fifo$29 ===

   Number of wires:                 30
   Number of wire bits:            155
   Number of public wires:          18
   Number of public wire bits:     123
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 19
     $add                            3
     $and                            4
     $mem_v2                         1
     $mux                            2
     $ne                             1
     $not                            2
     $reduce_bool                    2
     $sdffe                          3
     $sub                            1

=== fifo$37 ===

   Number of wires:                 30
   Number of wire bits:            155
   Number of public wires:          18
   Number of public wire bits:     123
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 19
     $add                            3
     $and                            4
     $mem_v2                         1
     $mux                            2
     $ne                             1
     $not                            2
     $reduce_bool                    2
     $sdffe                          3
     $sub                            1

=== fifo$45 ===

   Number of wires:                 30
   Number of wire bits:            155
   Number of public wires:          18
   Number of public wire bits:     123
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 19
     $add                            3
     $and                            4
     $mem_v2                         1
     $mux                            2
     $ne                             1
     $not                            2
     $reduce_bool                    2
     $sdffe                          3
     $sub                            1

=== fifo$53 ===

   Number of wires:                 30
   Number of wire bits:            155
   Number of public wires:          18
   Number of public wire bits:     123
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 19
     $add                            3
     $and                            4
     $mem_v2                         1
     $mux                            2
     $ne                             1
     $not                            2
     $reduce_bool                    2
     $sdffe                          3
     $sub                            1

=== fifo$61 ===

   Number of wires:                 30
   Number of wire bits:            155
   Number of public wires:          18
   Number of public wire bits:     123
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 19
     $add                            3
     $and                            4
     $mem_v2                         1
     $mux                            2
     $ne                             1
     $not                            2
     $reduce_bool                    2
     $sdffe                          3
     $sub                            1

=== init ===

   Number of wires:                 13
   Number of wire bits:             13
   Number of public wires:          11
   Number of public wire bits:      11
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  7
     $and                            1
     $not                            2
     $sdff                           1
     DDRDLLA                         1
     U$$1                            1
     U$$2                            1

=== lookahead_slicer ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== lookahead_slicer$15 ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== lookahead_slicer$23 ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== lookahead_slicer$31 ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== lookahead_slicer$39 ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== lookahead_slicer$47 ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== lookahead_slicer$55 ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== lookahead_slicer$7 ===

   Number of wires:                  3
   Number of wire bits:             43
   Number of public wires:           3
   Number of public wire bits:      43
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== multiplexer ===

   Number of wires:                258
   Number of wire bits:           1090
   Number of public wires:         180
   Number of public wire bits:     937
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                125
     $and                           24
     $eq                            15
     $logic_not                      1
     $mux                           38
     $ne                             6
     $not                            6
     $or                            17
     $reduce_and                     2
     $reduce_bool                    1
     $reduce_or                      5
     $sdffe                          1
     choose_cmd                      1
     choose_req                      1
     read_antistarvation             1
     steerer                         1
     tccdcon                         1
     tfawcon                         1
     trrdcon                         1
     twtrcon                         1
     write_antistarvation            1

=== phase_0 ===

   Number of wires:                 21
   Number of wire bits:            313
   Number of public wires:          20
   Number of public wire bits:     312
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  8
     $and                            2
     $mux                            4
     $not                            1
     $sdffe                          1

=== phase_1 ===

   Number of wires:                 21
   Number of wire bits:            313
   Number of public wires:          20
   Number of public wire bits:     312
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  8
     $and                            2
     $mux                            4
     $not                            1
     $sdffe                          1

=== pin_clk100_0 ===

   Number of wires:                  2
   Number of wire bits:              2
   Number of public wires:           2
   Number of public wire bits:       2
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     IB                              1

=== pin_ddr3_0__a ===

   Number of wires:                  9
   Number of wire bits:             81
   Number of public wires:           9
   Number of public wire bits:      81
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 26
     OB                             13
     ODDRX2F                        13

=== pin_ddr3_0__ba ===

   Number of wires:                  9
   Number of wire bits:             21
   Number of public wires:           9
   Number of public wire bits:      21
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  6
     OB                              3
     ODDRX2F                         3

=== pin_ddr3_0__cas ===

   Number of wires:                 13
   Number of wire bits:             13
   Number of public wires:          13
   Number of public wire bits:      13
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  6
     $not                            4
     OB                              1
     ODDRX2F                         1

=== pin_ddr3_0__clk ===

   Number of wires:                  9
   Number of wire bits:              9
   Number of public wires:           9
   Number of public wire bits:       9
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     OB                              1
     ODDRX2F                         1

=== pin_ddr3_0__clk_en ===

   Number of wires:                  9
   Number of wire bits:              9
   Number of public wires:           9
   Number of public wire bits:       9
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     OB                              1
     ODDRX2F                         1

=== pin_ddr3_0__cs ===

   Number of wires:                 13
   Number of wire bits:             13
   Number of public wires:          13
   Number of public wire bits:      13
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  6
     $not                            4
     OB                              1
     ODDRX2F                         1

=== pin_ddr3_0__dm ===

   Number of wires:                  2
   Number of wire bits:              4
   Number of public wires:           2
   Number of public wire bits:       4
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     OB                              2

=== pin_ddr3_0__odt ===

   Number of wires:                  9
   Number of wire bits:              9
   Number of public wires:           9
   Number of public wire bits:       9
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     OB                              1
     ODDRX2F                         1

=== pin_ddr3_0__ras ===

   Number of wires:                 13
   Number of wire bits:             13
   Number of public wires:          13
   Number of public wire bits:      13
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  6
     $not                            4
     OB                              1
     ODDRX2F                         1

=== pin_ddr3_0__rst ===

   Number of wires:                 13
   Number of wire bits:             13
   Number of public wires:          13
   Number of public wire bits:      13
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  6
     $not                            4
     OB                              1
     ODDRX2F                         1

=== pin_ddr3_0__we ===

   Number of wires:                 13
   Number of wire bits:             13
   Number of public wires:          13
   Number of public wire bits:      13
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  6
     $not                            4
     OB                              1
     ODDRX2F                         1

=== pin_rst_0 ===

   Number of wires:                  3
   Number of wire bits:              3
   Number of public wires:           3
   Number of public wire bits:       3
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     $not                            1
     IB                              1

=== pin_wishbone_0__ack ===

   Number of wires:                  2
   Number of wire bits:              2
   Number of public wires:           2
   Number of public wire bits:       2
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     OB                              1

=== pin_wishbone_0__adr ===

   Number of wires:                  2
   Number of wire bits:             64
   Number of public wires:           2
   Number of public wire bits:      64
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 32
     IB                             32

=== pin_wishbone_0__cyc ===

   Number of wires:                  2
   Number of wire bits:              2
   Number of public wires:           2
   Number of public wire bits:       2
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     IB                              1

=== pin_wishbone_0__dat_r ===

   Number of wires:                  2
   Number of wire bits:             64
   Number of public wires:           2
   Number of public wire bits:      64
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 32
     OB                             32

=== pin_wishbone_0__dat_w ===

   Number of wires:                  2
   Number of wire bits:             64
   Number of public wires:           2
   Number of public wire bits:      64
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 32
     IB                             32

=== pin_wishbone_0__sel ===

   Number of wires:                  2
   Number of wire bits:              8
   Number of public wires:           2
   Number of public wire bits:       8
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  4
     IB                              4

=== pin_wishbone_0__stb ===

   Number of wires:                  2
   Number of wire bits:              2
   Number of public wires:           2
   Number of public wire bits:       2
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     IB                              1

=== pin_wishbone_0__we ===

   Number of wires:                  2
   Number of wire bits:              2
   Number of public wires:           2
   Number of public wire bits:       2
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     IB                              1

=== pll ===

   Number of wires:                  7
   Number of wire bits:              7
   Number of public wires:           5
   Number of public wire bits:       5
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     $not                            1
     EHXPLLL                         1

=== postponer ===

   Number of wires:                 10
   Number of wire bits:             11
   Number of public wires:           5
   Number of public wire bits:       5
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  7
     $mux                            2
     $not                            1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          1
     $sub                            1

=== read_antistarvation ===

   Number of wires:                 14
   Number of wire bits:             31
   Number of public wires:           5
   Number of public wire bits:       9
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            5
     $ne                             1
     $reduce_bool                    1
     $sdffe                          2
     $sub                            1

=== refresher ===

   Number of wires:                 58
   Number of wire bits:             96
   Number of public wires:          27
   Number of public wire bits:      56
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 43
     $and                            1
     $eq                             3
     $logic_not                      1
     $mux                           22
     $ne                             4
     $not                            3
     $or                             1
     $reduce_and                     1
     $reduce_bool                    1
     $sdffe                          1
     postponer                       1
     sequencer                       1
     timer                           1
     zqcs_executer                   1
     zqcs_timer                      1

=== sequencer ===

   Number of wires:                 24
   Number of wire bits:             53
   Number of public wires:          19
   Number of public wire bits:      47
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $and                            1
     $mux                            3
     $or                             1
     $reduce_or                      1
     $sdffe                          3
     $sub                            1
     executer                        1

=== steerer ===

   Number of wires:                119
   Number of wire bits:            289
   Number of public wires:          55
   Number of public wire bits:     139
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 78
     $and                           16
     $dff                            1
     $eq                             4
     $logic_not                      2
     $mux                           35
     $not                            2
     $or                             2
     $reduce_or                      2
     $sdff                          14

=== sysclk ===

   Number of wires:                 24
   Number of wire bits:             29
   Number of public wires:          20
   Number of public wire bits:      22
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 16
     $dff                            1
     $dffe                           1
     $logic_not                      1
     $not                            2
     $or                             1
     $reduce_bool                    1
     $sub                            1
     CLKDIVF                         2
     ECLKSYNCB                       2
     FD1S3AX                         2
     SGSR                            1
     pll                             1

=== tccdcon ===

   Number of wires:                 12
   Number of wire bits:             13
   Number of public wires:           5
   Number of public wire bits:       5
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  9
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          1
     $sub                            1

=== tfawcon ===

   Number of wires:                 14
   Number of wire bits:             30
   Number of public wires:           6
   Number of public wire bits:      12
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 10
     $add                            4
     $eq                             1
     $lt                             1
     $mux                            1
     $not                            1
     $sdff                           1
     $sdffe                          1

=== timeline ===

   Number of wires:                 26
   Number of wire bits:             65
   Number of public wires:          10
   Number of public wire bits:      30
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 21
     $add                            1
     $and                            1
     $eq                             2
     $logic_not                      1
     $mux                            6
     $reduce_bool                    3
     $reduce_or                      2
     $sdffe                          5

=== timeline$5 ===

   Number of wires:                 28
   Number of wire bits:             63
   Number of public wires:          10
   Number of public wire bits:      29
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 22
     $add                            1
     $and                            1
     $eq                             2
     $logic_not                      1
     $mux                            7
     $reduce_bool                    4
     $reduce_or                      2
     $sdffe                          4

=== timer ===

   Number of wires:                 11
   Number of wire bits:             30
   Number of public wires:           5
   Number of public wire bits:      14
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  8
     $and                            1
     $eq                             1
     $not                            1
     $reduce_bool                    1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          1
     $sub                            1

=== top ===

   Number of wires:                179
   Number of wire bits:           1365
   Number of public wires:         179
   Number of public wire bits:    1365
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 26
     ddrphy                          1
     decoder                         1
     drambone                        1
     dramcore                        1
     pin_clk100_0                    1
     pin_ddr3_0__a                   1
     pin_ddr3_0__ba                  1
     pin_ddr3_0__cas                 1
     pin_ddr3_0__clk                 1
     pin_ddr3_0__clk_en              1
     pin_ddr3_0__cs                  1
     pin_ddr3_0__dm                  1
     pin_ddr3_0__odt                 1
     pin_ddr3_0__ras                 1
     pin_ddr3_0__rst                 1
     pin_ddr3_0__we                  1
     pin_rst_0                       1
     pin_wishbone_0__ack             1
     pin_wishbone_0__adr             1
     pin_wishbone_0__cyc             1
     pin_wishbone_0__dat_r           1
     pin_wishbone_0__dat_w           1
     pin_wishbone_0__sel             1
     pin_wishbone_0__stb             1
     pin_wishbone_0__we              1
     sysclk                          1

=== trascon ===

   Number of wires:                 13
   Number of wire bits:             18
   Number of public wires:           5
   Number of public wire bits:       6
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 10
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          1
     $sub                            1

=== trascon$11 ===

   Number of wires:                 13
   Number of wire bits:             18
   Number of public wires:           5
   Number of public wire bits:       6
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 10
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          1
     $sub                            1

=== trascon$19 ===

   Number of wires:                 13
   Number of wire bits:             18
   Number of public wires:           5
   Number of public wire bits:       6
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 10
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          1
     $sub                            1

=== trascon$27 ===

   Number of wires:                 13
   Number of wire bits:             18
   Number of public wires:           5
   Number of public wire bits:       6
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 10
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          1
     $sub                            1

=== trascon$35 ===

   Number of wires:                 13
   Number of wire bits:             18
   Number of public wires:           5
   Number of public wire bits:       6
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 10
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          1
     $sub                            1

=== trascon$43 ===

   Number of wires:                 13
   Number of wire bits:             18
   Number of public wires:           5
   Number of public wire bits:       6
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 10
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          1
     $sub                            1

=== trascon$51 ===

   Number of wires:                 13
   Number of wire bits:             18
   Number of public wires:           5
   Number of public wire bits:       6
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 10
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          1
     $sub                            1

=== trascon$59 ===

   Number of wires:                 13
   Number of wire bits:             18
   Number of public wires:           5
   Number of public wire bits:       6
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 10
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          1
     $sub                            1

=== trccon ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== trccon$10 ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== trccon$18 ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== trccon$26 ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== trccon$34 ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== trccon$42 ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== trccon$50 ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== trccon$58 ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== trrdcon ===

   Number of wires:                 12
   Number of wire bits:             13
   Number of public wires:           5
   Number of public wire bits:       5
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  9
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          1
     $sub                            1

=== twtpcon ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== twtpcon$17 ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== twtpcon$25 ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== twtpcon$33 ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== twtpcon$41 ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== twtpcon$49 ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== twtpcon$57 ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== twtpcon$9 ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== twtrcon ===

   Number of wires:                 13
   Number of wire bits:             22
   Number of public wires:           5
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            4
     $ne                             1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          2
     $sub                            1

=== wb_decoder ===

   Number of wires:                 16
   Number of wire bits:            149
   Number of public wires:          16
   Number of public wire bits:     149
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     $mux                            2

=== wb_decoder$4 ===

   Number of wires:                 16
   Number of wire bits:            155
   Number of public wires:          16
   Number of public wire bits:     155
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     $mux                            2

=== write_antistarvation ===

   Number of wires:                 14
   Number of wire bits:             27
   Number of public wires:           5
   Number of public wire bits:       8
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             1
     $mux                            5
     $ne                             1
     $reduce_bool                    1
     $sdffe                          2
     $sub                            1

=== zqcs_executer ===

   Number of wires:                 10
   Number of wire bits:             24
   Number of public wires:          10
   Number of public wire bits:      24
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     timeline$5                      1

=== zqcs_timer ===

   Number of wires:                 11
   Number of wire bits:             64
   Number of public wires:           5
   Number of public wire bits:      31
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  8
     $and                            1
     $eq                             1
     $not                            1
     $reduce_bool                    1
     $reduce_or                      1
     $sdff                           1
     $sdffe                          1
     $sub                            1

=== design hierarchy ===

   top                               1
     ddrphy                          1
       bridge                        1
         csr_bridge_0                1
         csr_mux_0                   1
         wb_decoder                  1
       dqsbufm_manager0              1
       dqsbufm_manager1              1
       init                          1
         U$$1                        1
         U$$2                        1
     decoder                         1
     drambone                        1
     dramcore                        1
       bridge$1                      1
         csr_bridge_0$3              1
         csr_mux_0$2                 1
         wb_decoder$4                1
       controller                    1
         bankmachine0                1
           U$$0                      1
             fifo                    1
           U$$1$6                    1
           current_slicer            1
           lookahead_slicer          1
           trascon                   1
           trccon                    1
           twtpcon                   1
         bankmachine1                1
           U$$0$12                   1
             fifo$13                 1
           U$$1$14                   1
           current_slicer$8          1
           lookahead_slicer$7        1
           trascon$11                1
           trccon$10                 1
           twtpcon$9                 1
         bankmachine2                1
           U$$0$20                   1
             fifo$21                 1
           U$$1$22                   1
           current_slicer$16         1
           lookahead_slicer$15       1
           trascon$19                1
           trccon$18                 1
           twtpcon$17                1
         bankmachine3                1
           U$$0$28                   1
             fifo$29                 1
           U$$1$30                   1
           current_slicer$24         1
           lookahead_slicer$23       1
           trascon$27                1
           trccon$26                 1
           twtpcon$25                1
         bankmachine4                1
           U$$0$36                   1
             fifo$37                 1
           U$$1$38                   1
           current_slicer$32         1
           lookahead_slicer$31       1
           trascon$35                1
           trccon$34                 1
           twtpcon$33                1
         bankmachine5                1
           U$$0$44                   1
             fifo$45                 1
           U$$1$46                   1
           current_slicer$40         1
           lookahead_slicer$39       1
           trascon$43                1
           trccon$42                 1
           twtpcon$41                1
         bankmachine6                1
           U$$0$52                   1
             fifo$53                 1
           U$$1$54                   1
           current_slicer$48         1
           lookahead_slicer$47       1
           trascon$51                1
           trccon$50                 1
           twtpcon$49                1
         bankmachine7                1
           U$$0$60                   1
             fifo$61                 1
           U$$1$62                   1
           current_slicer$56         1
           lookahead_slicer$55       1
           trascon$59                1
           trccon$58                 1
           twtpcon$57                1
         multiplexer                 1
           choose_cmd                1
             arbiter                 1
           choose_req                1
             arbiter$63              1
           read_antistarvation       1
           steerer                   1
           tccdcon                   1
           tfawcon                   1
           trrdcon                   1
           twtrcon                   1
           write_antistarvation      1
         refresher                   1
           postponer                 1
           sequencer                 1
             executer                1
               timeline              1
           timer                     1
           zqcs_executer             1
             timeline$5              1
           zqcs_timer                1
       crossbar                      1
         U$$8                        1
         U$$9                        1
       dfii                          1
         phase_0                     1
         phase_1                     1
     pin_clk100_0                    1
     pin_ddr3_0__a                   1
     pin_ddr3_0__ba                  1
     pin_ddr3_0__cas                 1
     pin_ddr3_0__clk                 1
     pin_ddr3_0__clk_en              1
     pin_ddr3_0__cs                  1
     pin_ddr3_0__dm                  1
     pin_ddr3_0__odt                 1
     pin_ddr3_0__ras                 1
     pin_ddr3_0__rst                 1
     pin_ddr3_0__we                  1
     pin_rst_0                       1
     pin_wishbone_0__ack             1
     pin_wishbone_0__adr             1
     pin_wishbone_0__cyc             1
     pin_wishbone_0__dat_r           1
     pin_wishbone_0__dat_w           1
     pin_wishbone_0__sel             1
     pin_wishbone_0__stb             1
     pin_wishbone_0__we              1
     sysclk                          1
       pll                           1

   Number of wires:               5545
   Number of wire bits:          24522
   Number of public wires:        3355
   Number of public wire bits:   19692
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               3172
     $add                           31
     $and                          233
     $dff                           42
     $dffe                           1
     $eq                           270
     $logic_not                     29
     $lt                             1
     $mem_v2                         8
     $mux                         1297
     $ne                           156
     $not                          131
     $or                           211
     $reduce_and                    69
     $reduce_bool                   50
     $reduce_or                     80
     $sdff                          66
     $sdffe                        200
     $sub                           42
     BB                             18
     CLKDIVF                         2
     DDRDLLA                         1
     DELAYG                         16
     DQSBUFM                         2
     ECLKSYNCB                       2
     EHXPLLL                         1
     FD1S3AX                         2
     IB                             73
     IDDRX2DQA                      16
     OB                             59
     ODDRX2DQA                      18
     ODDRX2DQSB                      2
     ODDRX2F                        24
     SGSR                            1
     TSHX2DQA                       16
     TSHX2DQSA                       2

End of script. Logfile hash: fd2a376567, CPU: user 4.36s system 0.00s, MEM: 41.62 MB peak
Yosys 0.13 (git sha1 8b1eafc3a, clang 7.0.1-8+deb10u2 -fPIC -Os)
Time spent: 25% 2x write_verilog (1 sec), 16% 3x opt_dff (0 sec), ...
patching file DDRDLLA.v

build_simsoc/top.v:5: warning: timescale for U$$0 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:95: warning: timescale for U$$0$12 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:185: warning: timescale for U$$0$20 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:275: warning: timescale for U$$0$28 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:365: warning: timescale for U$$0$36 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:455: warning: timescale for U$$0$44 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:545: warning: timescale for U$$0$52 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:635: warning: timescale for U$$0$60 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:725: warning: timescale for U$$0$64 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:740: warning: timescale for U$$1 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:768: warning: timescale for U$$1$14 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:813: warning: timescale for U$$1$22 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:858: warning: timescale for U$$1$30 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:903: warning: timescale for U$$1$38 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:948: warning: timescale for U$$1$46 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:993: warning: timescale for U$$1$54 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:1038: warning: timescale for U$$1$6 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:1083: warning: timescale for U$$1$62 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:1128: warning: timescale for U$$1$65 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:1143: warning: timescale for U$$2 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:1214: warning: timescale for U$$2$66 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:1229: warning: timescale for U$$3 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:1244: warning: timescale for U$$4 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:1259: warning: timescale for U$$5 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:1274: warning: timescale for U$$6 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:1289: warning: timescale for U$$7 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:1304: warning: timescale for U$$8 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:1323: warning: timescale for U$$9 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:1342: warning: timescale for arbiter inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:1539: warning: timescale for arbiter$63 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:1736: warning: timescale for bankmachine0 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:2160: warning: timescale for bankmachine1 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:2584: warning: timescale for bankmachine2 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:3008: warning: timescale for bankmachine3 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:3432: warning: timescale for bankmachine4 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:3856: warning: timescale for bankmachine5 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:4280: warning: timescale for bankmachine6 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:4704: warning: timescale for bankmachine7 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:5128: warning: timescale for bridge inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:5241: warning: timescale for bridge$1 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:5376: warning: timescale for choose_cmd inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:5840: warning: timescale for choose_req inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:6303: warning: timescale for controller inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:7201: warning: timescale for crossbar inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:7698: warning: timescale for csr_bridge_0 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:7863: warning: timescale for csr_bridge_0$3 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:8028: warning: timescale for csr_mux_0 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:8254: warning: timescale for csr_mux_0$2 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:8712: warning: timescale for current_slicer inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:8725: warning: timescale for current_slicer$16 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:8738: warning: timescale for current_slicer$24 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:8751: warning: timescale for current_slicer$32 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:8764: warning: timescale for current_slicer$40 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:8777: warning: timescale for current_slicer$48 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:8790: warning: timescale for current_slicer$56 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:8803: warning: timescale for current_slicer$8 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:8816: warning: timescale for ddrphy inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:10826: warning: timescale for decoder inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:10931: warning: timescale for dfii inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:11249: warning: timescale for dqsbufm_manager0 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:11333: warning: timescale for dqsbufm_manager1 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:11417: warning: timescale for drambone inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:11556: warning: timescale for dramcore inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:12348: warning: timescale for executer inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:12385: warning: timescale for fifo inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:12497: warning: timescale for fifo$13 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:12609: warning: timescale for fifo$21 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:12721: warning: timescale for fifo$29 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:12833: warning: timescale for fifo$37 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:12945: warning: timescale for fifo$45 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:13057: warning: timescale for fifo$53 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:13169: warning: timescale for fifo$61 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:13281: warning: timescale for init inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:13340: warning: timescale for lookahead_slicer inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:13354: warning: timescale for lookahead_slicer$15 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:13368: warning: timescale for lookahead_slicer$23 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:13382: warning: timescale for lookahead_slicer$31 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:13396: warning: timescale for lookahead_slicer$39 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:13410: warning: timescale for lookahead_slicer$47 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:13424: warning: timescale for lookahead_slicer$55 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:13438: warning: timescale for lookahead_slicer$7 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:13452: warning: timescale for multiplexer inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:14319: warning: timescale for phase_0 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:14381: warning: timescale for phase_1 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:14443: warning: timescale for pin_clk100_0 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:14456: warning: timescale for pin_ddr3_0__a inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:14661: warning: timescale for pin_ddr3_0__ba inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:14727: warning: timescale for pin_ddr3_0__cas inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:14776: warning: timescale for pin_ddr3_0__clk inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:14813: warning: timescale for pin_ddr3_0__clk_en inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:14850: warning: timescale for pin_ddr3_0__cs inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:14899: warning: timescale for pin_ddr3_0__dm inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:14916: warning: timescale for pin_ddr3_0__odt inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:14953: warning: timescale for pin_ddr3_0__ras inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15002: warning: timescale for pin_ddr3_0__rst inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15051: warning: timescale for pin_ddr3_0__we inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15100: warning: timescale for pin_rst_0 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15116: warning: timescale for pin_wishbone_0__ack inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15129: warning: timescale for pin_wishbone_0__adr inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15266: warning: timescale for pin_wishbone_0__cyc inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15279: warning: timescale for pin_wishbone_0__dat_r inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15416: warning: timescale for pin_wishbone_0__dat_w inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15553: warning: timescale for pin_wishbone_0__sel inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15578: warning: timescale for pin_wishbone_0__stb inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15591: warning: timescale for pin_wishbone_0__we inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15604: warning: timescale for pll inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15655: warning: timescale for postponer inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15689: warning: timescale for read_antistarvation inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15733: warning: timescale for refresher inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15907: warning: timescale for sequencer inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:15999: warning: timescale for steerer inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:16332: warning: timescale for sysclk inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:16452: warning: timescale for tccdcon inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:16491: warning: timescale for tfawcon inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:16541: warning: timescale for timeline inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:16629: warning: timescale for timeline$5 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:16718: warning: timescale for timer inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:16758: warning: timescale for top inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:17506: warning: timescale for trascon inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:17548: warning: timescale for trascon$11 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:17590: warning: timescale for trascon$19 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:17632: warning: timescale for trascon$27 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:17674: warning: timescale for trascon$35 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:17716: warning: timescale for trascon$43 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:17758: warning: timescale for trascon$51 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:17800: warning: timescale for trascon$59 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:17842: warning: timescale for trccon inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:17893: warning: timescale for trccon$10 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:17944: warning: timescale for trccon$18 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:17995: warning: timescale for trccon$26 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18046: warning: timescale for trccon$34 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18097: warning: timescale for trccon$42 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18148: warning: timescale for trccon$50 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18199: warning: timescale for trccon$58 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18250: warning: timescale for trrdcon inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18289: warning: timescale for twtpcon inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18335: warning: timescale for twtpcon$17 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18381: warning: timescale for twtpcon$25 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18427: warning: timescale for twtpcon$33 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18473: warning: timescale for twtpcon$41 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18519: warning: timescale for twtpcon$49 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18565: warning: timescale for twtpcon$57 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18611: warning: timescale for twtpcon$9 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18657: warning: timescale for twtrcon inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18703: warning: timescale for wb_decoder inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18748: warning: timescale for wb_decoder$4 inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18793: warning: timescale for write_antistarvation inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18837: warning: timescale for zqcs_executer inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
build_simsoc/top.v:18874: warning: timescale for zqcs_timer inherited from another file.
simsoctb.v:3: ...: The inherited timescale is here.
/home/isengaara/Hacking/libre-soc/ecp5u/EHXPLLL.v:88: warning: implicit definition of wire 'CLKIB'.
/home/isengaara/Hacking/libre-soc/ecp5u/EHXPLLL.v:89: warning: implicit definition of wire 'FBB'.
/home/isengaara/Hacking/libre-soc/ecp5u/EHXPLLL.v:90: warning: implicit definition of wire 'RSTB'.
/home/isengaara/Hacking/libre-soc/ecp5u/EHXPLLL.v:93: warning: implicit definition of wire 'PHASEDIRB'.
/home/isengaara/Hacking/libre-soc/ecp5u/EHXPLLL.v:545: warning: implicit definition of wire 'refclk'.
/home/isengaara/Hacking/libre-soc/ecp5u/EHXPLLL.v:551: warning: implicit definition of wire 'clkib'.
/home/isengaara/Hacking/libre-soc/ecp5u/EHXPLLL.v:552: warning: implicit definition of wire 'fbb'.
/home/isengaara/Hacking/libre-soc/ecp5u/EHXPLLL.v:553: warning: implicit definition of wire 'rstb'.
/home/isengaara/Hacking/libre-soc/ecp5u/EHXPLLL.v:561: warning: implicit definition of wire 'phasedirb'.
/home/isengaara/Hacking/libre-soc/ecp5u/EHXPLLL.v:562: warning: implicit definition of wire 'phasestepb'.
/home/isengaara/Hacking/libre-soc/ecp5u/EHXPLLL.v:565: warning: implicit definition of wire 'phasesrcstat'.
/home/isengaara/Hacking/libre-soc/ecp5u/EHXPLLL.v:1925: warning: implicit definition of wire 'rstb_old'.
/home/isengaara/Hacking/libre-soc/ecp5u/FD1S3AX.v:49: warning: implicit definition of wire 'SR'.
/home/isengaara/Hacking/libre-soc/ecp5u/ODDRX2F.v:111: warning: implicit definition of wire 'SR'.
/home/isengaara/Hacking/libre-soc/ecp5u/ODDRX2DQA.v:130: warning: implicit definition of wire 'SR'.
/home/isengaara/Hacking/libre-soc/ecp5u/BB.v:39: warning: implicit definition of wire 'TN'.
/home/isengaara/Hacking/libre-soc/ecp5u/BB.v:40: warning: implicit definition of wire 'ENH'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:113: warning: implicit definition of wire 'RSTB1'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:116: warning: implicit definition of wire 'ECLKB'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:117: warning: implicit definition of wire 'READ0B'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:118: warning: implicit definition of wire 'READ1B'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:119: warning: implicit definition of wire 'READCLKSEL2B'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:122: warning: implicit definition of wire 'DDRDELB'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:131: warning: implicit definition of wire 'WRLOADNB'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:132: warning: implicit definition of wire 'RDLOADNB'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:133: warning: implicit definition of wire 'RDMOVEB'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:134: warning: implicit definition of wire 'RDDIRECTIONB'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:135: warning: implicit definition of wire 'WRMOVEB'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:136: warning: implicit definition of wire 'WRDIRECTIONB'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:137: warning: implicit definition of wire 'PAUSEB'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:215: warning: implicit definition of wire 'SR'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:216: warning: implicit definition of wire 'RSTB2'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:511: warning: implicit definition of wire 'read_posti_del'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:689: warning: implicit definition of wire 'dqs_ena_del'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:1055: warning: implicit definition of wire 'rd_ne_wr'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:1056: warning: implicit definition of wire 'rdp1_ne_wr'.
/home/isengaara/Hacking/libre-soc/ecp5u/DQSBUFM.v:1057: warning: implicit definition of wire 'move'.
/home/isengaara/Hacking/libre-soc/ecp5u/TSHX2DQSA.v:53: warning: implicit definition of wire 'RSTB1'.
/home/isengaara/Hacking/libre-soc/ecp5u/TSHX2DQSA.v:97: warning: implicit definition of wire 'SR'.
/home/isengaara/Hacking/libre-soc/ecp5u/TSHX2DQSA.v:98: warning: implicit definition of wire 'RSTB2'.
/home/isengaara/Hacking/libre-soc/ecp5u/TSHX2DQA.v:53: warning: implicit definition of wire 'RSTB1'.
/home/isengaara/Hacking/libre-soc/ecp5u/TSHX2DQA.v:97: warning: implicit definition of wire 'SR'.
/home/isengaara/Hacking/libre-soc/ecp5u/TSHX2DQA.v:98: warning: implicit definition of wire 'RSTB2'.
/home/isengaara/Hacking/libre-soc/ecp5u/ODDRX2DQSB.v:129: warning: implicit definition of wire 'SR'.
/home/isengaara/Hacking/libre-soc/ecp5u/IDDRX2DQA.v:69: warning: implicit definition of wire 'DQSR90B'.
/home/isengaara/Hacking/libre-soc/ecp5u/IDDRX2DQA.v:156: warning: implicit definition of wire 'SR'.
/home/isengaara/Hacking/libre-soc/ecp5u/IDDRX2DQA.v:230: warning: implicit definition of wire 'slip_rst'.
/home/isengaara/Hacking/libre-soc/ecp5u/IDDRX2DQA.v:231: warning: implicit definition of wire 'slip_trig'.
/home/isengaara/Hacking/libre-soc/ecp5u/IDDRX2DQA.v:232: warning: implicit definition of wire 'cnt_en'.
DDRDLLA.v:74: warning: implicit definition of wire 'RSTB1'.
DDRDLLA.v:108: warning: implicit definition of wire 'SR'.
/home/isengaara/Hacking/libre-soc/ecp5u/CLKDIVF.v:108: warning: implicit definition of wire 'SR1'.
/home/isengaara/Hacking/libre-soc/ecp5u/CLKDIVF.v:109: warning: implicit definition of wire 'RSTB2'.
/home/isengaara/Hacking/libre-soc/ecp5u/CLKDIVF.v:151: warning: implicit definition of wire 'slip_rst'.
/home/isengaara/Hacking/libre-soc/ecp5u/CLKDIVF.v:152: warning: implicit definition of wire 'slip_trig'.
dram_model/ddr3.v:1201: warning: Constant bit select [13] is after vector addr[12:0].
dram_model/ddr3.v:1201:        : Replacing select with a constant 1'bx.
dram_model/ddr3.v:1290: warning: Constant bit select [13] is after vector addr[12:0].
dram_model/ddr3.v:1290:        : Replacing select with a constant 1'bx.
dram_model/ddr3.v:1361: warning: Part select [13:11] is selecting after the vector addr[12:0].
dram_model/ddr3.v:1361:        : Replacing the out of bound bits with 'bx.
dram_model/ddr3.v:1391: warning: Part select [13:3] is selecting after the vector addr[12:0].
dram_model/ddr3.v:1391:        : Replacing the out of bound bits with 'bx.
dram_model/ddr3.v:548: error: expression not valid in assign l-value: ~(dqs)
simsoctb.v:48: warning: Port 11 (addr) of ddr3 expects 13 bits, got 14.
simsoctb.v:48:        : Pruning 1 high bits of the expression.
/home/isengaara/Hacking/libre-soc/ecp5u/EHXPLLL.v:217: warning: Instantiating module pll_pll with dangling input port 94 (mc1_no_pllreset) floating.
build_simsoc/top.v:15643: warning: Instantiating module EHXPLLL with dangling input port 2 (CLKFB) floating.
build_simsoc/top.v:15643: warning: Instantiating module EHXPLLL with dangling input port 3 (PHASESEL1) floating.
build_simsoc/top.v:15643: warning: Instantiating module EHXPLLL with dangling input port 4 (PHASESEL0) floating.
build_simsoc/top.v:15643: warning: Instantiating module EHXPLLL with dangling input port 5 (PHASEDIR) floating.
build_simsoc/top.v:15643: warning: Instantiating module EHXPLLL with dangling input port 6 (PHASESTEP) floating.
build_simsoc/top.v:15643: warning: Instantiating module EHXPLLL with dangling input port 7 (PHASELOADREG) floating.
build_simsoc/top.v:15643: warning: Instantiating module EHXPLLL with dangling input port 8 (STDBY) floating.
build_simsoc/top.v:15643: warning: Instantiating module EHXPLLL with dangling input port 9 (PLLWAKESYNC) floating.
build_simsoc/top.v:15643: warning: Instantiating module EHXPLLL with dangling input port 11 (ENCLKOP) floating.
build_simsoc/top.v:15643: warning: Instantiating module EHXPLLL with dangling input port 12 (ENCLKOS) floating.
build_simsoc/top.v:15643: warning: Instantiating module EHXPLLL with dangling input port 13 (ENCLKOS2) floating.
build_simsoc/top.v:15643: warning: Instantiating module EHXPLLL with dangling input port 14 (ENCLKOS3) floating.
simsoctb.v:81: warning: Port 9 (ddr3_0__a__io) of top expects 13 bits, got 14.
simsoctb.v:81:        : Padding 1 high bits of the expression.
TCK_MIN =        2500
simsoctb.ram_chip.file_io_open: at time                    0 WARNING: no +model_data option specified, using /tmp.
simsoctb.ram_chip.open_bank_file: at time 0 INFO: opening /tmp/simsoctb.ram_chip.open_bank_file.0.
simsoctb.ram_chip.open_bank_file: at time 0 INFO: opening /tmp/simsoctb.ram_chip.open_bank_file.1.
simsoctb.ram_chip.open_bank_file: at time 0 INFO: opening /tmp/simsoctb.ram_chip.open_bank_file.2.
simsoctb.ram_chip.open_bank_file: at time 0 INFO: opening /tmp/simsoctb.ram_chip.open_bank_file.3.
simsoctb.ram_chip.open_bank_file: at time 0 INFO: opening /tmp/simsoctb.ram_chip.open_bank_file.4.
simsoctb.ram_chip.open_bank_file: at time 0 INFO: opening /tmp/simsoctb.ram_chip.open_bank_file.5.
simsoctb.ram_chip.open_bank_file: at time 0 INFO: opening /tmp/simsoctb.ram_chip.open_bank_file.6.
simsoctb.ram_chip.open_bank_file: at time 0 INFO: opening /tmp/simsoctb.ram_chip.open_bank_file.7.
MEMORY_WRITE: Bank = 0, Row = 0000, Col = 000, Data = 12345678faaffeef0a0a0a0afaceca8c
MEMORY_READ: Bank = 0, Row = 0000, Col = 000, Data = 12345678faaffeef0a0a0a0afaceca8c
MEMORY_WRITE: Bank = 0, Row = 0000, Col = 008, Data = 00000000111111112222222233333333
MEMORY_READ: Bank = 0, Row = 0000, Col = 008, Data = 00000000111111112222222233333333
MEMORY_WRITE: Bank = 0, Row = 0000, Col = 010, Data = f00df00d0102030455556666a0a0a0a0
MEMORY_READ: Bank = 0, Row = 0000, Col = 010, Data = f00df00d0102030455556666a0a0a0a0
MEMORY_WRITE: Bank = 0, Row = 0000, Col = 018, Data = c0cac0ca000caca0000c0c0aaaaaaaaa
MEMORY_READ: Bank = 0, Row = 0000, Col = 018, Data = c0cac0ca000caca0000c0c0aaaaaaaaa
MEMORY_WRITE: Bank = 0, Row = 0000, Col = 018, Data = c0cac0ca000caca0000c0c0aaaaaaaaa
MEMORY_READ: Bank = 0, Row = 0000, Col = 018, Data = c0cac0ca000caca0000c0c0aaaaaaaaa
FST info: dumpfile simsoc.fst opened for output.
Release RESET_N
Enable CKE
Set MR2
Set MR3
[845000.0 ps] cmd_task Load Mode
simsoctb.ram_chip.cmd_task: at time 845000.0 ps INFO: Load Mode 2
simsoctb.ram_chip.cmd_task: at time 845000.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
simsoctb.ram_chip.cmd_task: at time 845000.0 ps INFO: Load Mode 2 CAS Write Latency =           5
simsoctb.ram_chip.cmd_task: at time 845000.0 ps INFO: Load Mode 2 Auto Self Refresh = Disabled
simsoctb.ram_chip.cmd_task: at time 845000.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
simsoctb.ram_chip.cmd_task: at time 845000.0 ps INFO: Load Mode 2 Dynamic ODT Rtt =          60 Ohm
Set MR1
[1085000.0 ps] cmd_task Load Mode
simsoctb.ram_chip.cmd_task: at time 1085000.0 ps INFO: Load Mode 3
simsoctb.ram_chip.cmd_task: at time 1085000.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
simsoctb.ram_chip.cmd_task: at time 1085000.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
Set MR0
[1325000.0 ps] cmd_task Load Mode
simsoctb.ram_chip.cmd_task: at time 1325000.0 ps INFO: Load Mode 1
simsoctb.ram_chip.cmd_task: at time 1325000.0 ps INFO: Load Mode 1 DLL Enable = Enabled
simsoctb.ram_chip.cmd_task: at time 1325000.0 ps INFO: Load Mode 1 Output Drive Strength =          34 Ohm
simsoctb.ram_chip.cmd_task: at time 1325000.0 ps INFO: Load Mode 1 ODT Rtt =          60 Ohm
simsoctb.ram_chip.cmd_task: at time 1325000.0 ps INFO: Load Mode 1 Additive Latency = 0
simsoctb.ram_chip.cmd_task: at time 1325000.0 ps INFO: Load Mode 1 Write Levelization = Disabled
simsoctb.ram_chip.cmd_task: at time 1325000.0 ps INFO: Load Mode 1 TDQS Enable = Disabled
simsoctb.ram_chip.cmd_task: at time 1325000.0 ps INFO: Load Mode 1 Qoff = Enabled
[1565000.0 ps] cmd_task Load Mode
simsoctb.ram_chip.cmd_task: at time 1565000.0 ps INFO: Load Mode 0
simsoctb.ram_chip.cmd_task: at time 1565000.0 ps INFO: Load Mode 0 Burst Length =  8
simsoctb.ram_chip.cmd_task: at time 1565000.0 ps INFO: Load Mode 0 Burst Order = Sequential
simsoctb.ram_chip.cmd_task: at time 1565000.0 ps INFO: Load Mode 0 CAS Latency =           6
simsoctb.ram_chip.cmd_task: at time 1565000.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
simsoctb.ram_chip.cmd_task: at time 1565000.0 ps INFO: Load Mode 0 Write Recovery =           5
simsoctb.ram_chip.cmd_task: at time 1565000.0 ps INFO: Load Mode 0 Power Down Mode = DLL off
[1805000.0 ps] cmd_task Load Mode
simsoctb.ram_chip.cmd_task: at time 1805000.0 ps INFO: Load Mode 0
simsoctb.ram_chip.cmd_task: at time 1805000.0 ps INFO: Load Mode 0 Burst Length =  8
simsoctb.ram_chip.cmd_task: at time 1805000.0 ps INFO: Load Mode 0 Burst Order = Sequential
simsoctb.ram_chip.cmd_task: at time 1805000.0 ps INFO: Load Mode 0 CAS Latency =           6
simsoctb.ram_chip.cmd_task: at time 1805000.0 ps INFO: Load Mode 0 DLL Reset = Normal
simsoctb.ram_chip.cmd_task: at time 1805000.0 ps INFO: Load Mode 0 Write Recovery =           5
simsoctb.ram_chip.cmd_task: at time 1805000.0 ps INFO: Load Mode 0 Power Down Mode = DLL off
Start ZQ calibration
[8045000.0 ps] cmd_task ZQ       
simsoctb.ram_chip.cmd_task: at time 8045000.0 ps INFO: ZQ        long = 1
simsoctb.ram_chip.cmd_task: at time 8045000.0 ps INFO: Initialization Sequence is complete
[16170000.0 ps] cmd_task Activate 
simsoctb.ram_chip.cmd_task: at time 16170000.0 ps INFO: Activate  bank 0 row 0000
[16185000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 16185000.0 ps INFO: Read      bank 0 col 000, auto precharge 0
simsoctb.ram_chip.data_task: at time 16212500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = ca8c
simsoctb.ram_chip.data_task: at time 16215000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = face
simsoctb.ram_chip.data_task: at time 16217500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 0a0a
simsoctb.ram_chip.data_task: at time 16220000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 0a0a
simsoctb.ram_chip.data_task: at time 16222500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = feef
simsoctb.ram_chip.data_task: at time 16225000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = faaf
simsoctb.ram_chip.data_task: at time 16227500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 5678
simsoctb.ram_chip.data_task: at time 16230000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 1234
[16355000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 16355000.0 ps INFO: Read      bank 0 col 000, auto precharge 0
simsoctb.ram_chip.data_task: at time 16382500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = ca8c
simsoctb.ram_chip.data_task: at time 16385000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = face
simsoctb.ram_chip.data_task: at time 16387500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 0a0a
simsoctb.ram_chip.data_task: at time 16390000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 0a0a
simsoctb.ram_chip.data_task: at time 16392500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = feef
simsoctb.ram_chip.data_task: at time 16395000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = faaf
simsoctb.ram_chip.data_task: at time 16397500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 5678
simsoctb.ram_chip.data_task: at time 16400000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 1234
[16525000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 16525000.0 ps INFO: Read      bank 0 col 000, auto precharge 0
simsoctb.ram_chip.data_task: at time 16552500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = ca8c
simsoctb.ram_chip.data_task: at time 16555000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = face
simsoctb.ram_chip.data_task: at time 16557500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 0a0a
simsoctb.ram_chip.data_task: at time 16560000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 0a0a
simsoctb.ram_chip.data_task: at time 16562500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = feef
simsoctb.ram_chip.data_task: at time 16565000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = faaf
simsoctb.ram_chip.data_task: at time 16567500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 5678
simsoctb.ram_chip.data_task: at time 16570000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 1234
[16695000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 16695000.0 ps INFO: Read      bank 0 col 000, auto precharge 0
simsoctb.ram_chip.data_task: at time 16722500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = ca8c
simsoctb.ram_chip.data_task: at time 16725000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = face
simsoctb.ram_chip.data_task: at time 16727500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 0a0a
simsoctb.ram_chip.data_task: at time 16730000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 0a0a
simsoctb.ram_chip.data_task: at time 16732500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = feef
simsoctb.ram_chip.data_task: at time 16735000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = faaf
simsoctb.ram_chip.data_task: at time 16737500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 5678
simsoctb.ram_chip.data_task: at time 16740000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 1234
[16865000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 16865000.0 ps INFO: Read      bank 0 col 008, auto precharge 0
simsoctb.ram_chip.data_task: at time 16892500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 3333
simsoctb.ram_chip.data_task: at time 16895000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 3333
simsoctb.ram_chip.data_task: at time 16897500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 2222
simsoctb.ram_chip.data_task: at time 16900000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 2222
simsoctb.ram_chip.data_task: at time 16902500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 1111
simsoctb.ram_chip.data_task: at time 16905000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 1111
simsoctb.ram_chip.data_task: at time 16907500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 0000
simsoctb.ram_chip.data_task: at time 16910000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 0000
[17035000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 17035000.0 ps INFO: Read      bank 0 col 008, auto precharge 0
simsoctb.ram_chip.data_task: at time 17062500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 3333
simsoctb.ram_chip.data_task: at time 17065000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 3333
simsoctb.ram_chip.data_task: at time 17067500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 2222
simsoctb.ram_chip.data_task: at time 17070000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 2222
simsoctb.ram_chip.data_task: at time 17072500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 1111
simsoctb.ram_chip.data_task: at time 17075000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 1111
simsoctb.ram_chip.data_task: at time 17077500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 0000
simsoctb.ram_chip.data_task: at time 17080000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 0000
[17205000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 17205000.0 ps INFO: Read      bank 0 col 008, auto precharge 0
simsoctb.ram_chip.data_task: at time 17232500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 3333
simsoctb.ram_chip.data_task: at time 17235000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 3333
simsoctb.ram_chip.data_task: at time 17237500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 2222
simsoctb.ram_chip.data_task: at time 17240000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 2222
simsoctb.ram_chip.data_task: at time 17242500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 1111
simsoctb.ram_chip.data_task: at time 17245000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 1111
simsoctb.ram_chip.data_task: at time 17247500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 0000
simsoctb.ram_chip.data_task: at time 17250000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 0000
[17375000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 17375000.0 ps INFO: Read      bank 0 col 008, auto precharge 0
simsoctb.ram_chip.data_task: at time 17402500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 3333
simsoctb.ram_chip.data_task: at time 17405000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 3333
simsoctb.ram_chip.data_task: at time 17407500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 2222
simsoctb.ram_chip.data_task: at time 17410000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 2222
simsoctb.ram_chip.data_task: at time 17412500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 1111
simsoctb.ram_chip.data_task: at time 17415000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 1111
simsoctb.ram_chip.data_task: at time 17417500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 0000
simsoctb.ram_chip.data_task: at time 17420000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 0000
[17545000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 17545000.0 ps INFO: Read      bank 0 col 010, auto precharge 0
simsoctb.ram_chip.data_task: at time 17572500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000010 data = a0a0
simsoctb.ram_chip.data_task: at time 17575000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000011 data = a0a0
simsoctb.ram_chip.data_task: at time 17577500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000012 data = 6666
simsoctb.ram_chip.data_task: at time 17580000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000013 data = 5555
simsoctb.ram_chip.data_task: at time 17582500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000014 data = 0304
simsoctb.ram_chip.data_task: at time 17585000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000015 data = 0102
simsoctb.ram_chip.data_task: at time 17587500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000016 data = f00d
simsoctb.ram_chip.data_task: at time 17590000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000017 data = f00d
[17715000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 17715000.0 ps INFO: Read      bank 0 col 010, auto precharge 0
simsoctb.ram_chip.data_task: at time 17742500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000010 data = a0a0
simsoctb.ram_chip.data_task: at time 17745000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000011 data = a0a0
simsoctb.ram_chip.data_task: at time 17747500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000012 data = 6666
simsoctb.ram_chip.data_task: at time 17750000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000013 data = 5555
simsoctb.ram_chip.data_task: at time 17752500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000014 data = 0304
simsoctb.ram_chip.data_task: at time 17755000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000015 data = 0102
simsoctb.ram_chip.data_task: at time 17757500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000016 data = f00d
simsoctb.ram_chip.data_task: at time 17760000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000017 data = f00d
[17885000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 17885000.0 ps INFO: Read      bank 0 col 010, auto precharge 0
simsoctb.ram_chip.data_task: at time 17912500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000010 data = a0a0
simsoctb.ram_chip.data_task: at time 17915000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000011 data = a0a0
simsoctb.ram_chip.data_task: at time 17917500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000012 data = 6666
simsoctb.ram_chip.data_task: at time 17920000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000013 data = 5555
simsoctb.ram_chip.data_task: at time 17922500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000014 data = 0304
simsoctb.ram_chip.data_task: at time 17925000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000015 data = 0102
simsoctb.ram_chip.data_task: at time 17927500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000016 data = f00d
simsoctb.ram_chip.data_task: at time 17930000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000017 data = f00d
[18055000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 18055000.0 ps INFO: Read      bank 0 col 010, auto precharge 0
simsoctb.ram_chip.data_task: at time 18082500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000010 data = a0a0
simsoctb.ram_chip.data_task: at time 18085000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000011 data = a0a0
simsoctb.ram_chip.data_task: at time 18087500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000012 data = 6666
simsoctb.ram_chip.data_task: at time 18090000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000013 data = 5555
simsoctb.ram_chip.data_task: at time 18092500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000014 data = 0304
simsoctb.ram_chip.data_task: at time 18095000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000015 data = 0102
simsoctb.ram_chip.data_task: at time 18097500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000016 data = f00d
simsoctb.ram_chip.data_task: at time 18100000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000017 data = f00d
[18225000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 18225000.0 ps INFO: Read      bank 0 col 018, auto precharge 0
simsoctb.ram_chip.data_task: at time 18252500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000018 data = aaaa
simsoctb.ram_chip.data_task: at time 18255000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000019 data = aaaa
simsoctb.ram_chip.data_task: at time 18257500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001a data = 0c0a
simsoctb.ram_chip.data_task: at time 18260000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001b data = 000c
simsoctb.ram_chip.data_task: at time 18262500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001c data = aca0
simsoctb.ram_chip.data_task: at time 18265000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001d data = 000c
simsoctb.ram_chip.data_task: at time 18267500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001e data = c0ca
simsoctb.ram_chip.data_task: at time 18270000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001f data = c0ca
[18395000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 18395000.0 ps INFO: Read      bank 0 col 018, auto precharge 0
simsoctb.ram_chip.data_task: at time 18422500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000018 data = aaaa
simsoctb.ram_chip.data_task: at time 18425000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000019 data = aaaa
simsoctb.ram_chip.data_task: at time 18427500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001a data = 0c0a
simsoctb.ram_chip.data_task: at time 18430000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001b data = 000c
simsoctb.ram_chip.data_task: at time 18432500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001c data = aca0
simsoctb.ram_chip.data_task: at time 18435000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001d data = 000c
simsoctb.ram_chip.data_task: at time 18437500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001e data = c0ca
simsoctb.ram_chip.data_task: at time 18440000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001f data = c0ca
[18565000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 18565000.0 ps INFO: Read      bank 0 col 018, auto precharge 0
simsoctb.ram_chip.data_task: at time 18592500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000018 data = aaaa
simsoctb.ram_chip.data_task: at time 18595000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000019 data = aaaa
simsoctb.ram_chip.data_task: at time 18597500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001a data = 0c0a
simsoctb.ram_chip.data_task: at time 18600000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001b data = 000c
simsoctb.ram_chip.data_task: at time 18602500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001c data = aca0
simsoctb.ram_chip.data_task: at time 18605000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001d data = 000c
simsoctb.ram_chip.data_task: at time 18607500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001e data = c0ca
simsoctb.ram_chip.data_task: at time 18610000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001f data = c0ca
[18735000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 18735000.0 ps INFO: Read      bank 0 col 018, auto precharge 0
simsoctb.ram_chip.data_task: at time 18762500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000018 data = aaaa
simsoctb.ram_chip.data_task: at time 18765000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000019 data = aaaa
simsoctb.ram_chip.data_task: at time 18767500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001a data = 0c0a
simsoctb.ram_chip.data_task: at time 18770000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001b data = 000c
simsoctb.ram_chip.data_task: at time 18772500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001c data = aca0
simsoctb.ram_chip.data_task: at time 18775000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001d data = 000c
simsoctb.ram_chip.data_task: at time 18777500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001e data = c0ca
simsoctb.ram_chip.data_task: at time 18780000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000001f data = c0ca
[19040000.0 ps] cmd_task Write    
simsoctb.ram_chip.cmd_task: at time 19040000.0 ps INFO: Write     bank 0 col 000, auto precharge 0
simsoctb.ram_chip.data_task: at time 19067500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = ca8c
simsoctb.ram_chip.data_task: at time 19070000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = face
simsoctb.ram_chip.data_task: at time 19072500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 0a0a
simsoctb.ram_chip.data_task: at time 19075000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 0a0a
simsoctb.ram_chip.data_task: at time 19077500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = feef
simsoctb.ram_chip.data_task: at time 19080000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = faaf
simsoctb.ram_chip.data_task: at time 19082500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 0bab
simsoctb.ram_chip.data_task: at time 19085000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 00ba
[19110000.0 ps] cmd_task Write    
simsoctb.ram_chip.cmd_task: at time 19110000.0 ps INFO: Write     bank 0 col 000, auto precharge 0
simsoctb.ram_chip.data_task: at time 19137500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = ca8c
simsoctb.ram_chip.data_task: at time 19140000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = face
simsoctb.ram_chip.data_task: at time 19142500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 0a0a
simsoctb.ram_chip.data_task: at time 19145000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 0a0a
simsoctb.ram_chip.data_task: at time 19147500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 4242
simsoctb.ram_chip.data_task: at time 19150000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 1337
simsoctb.ram_chip.data_task: at time 19152500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 0bab
simsoctb.ram_chip.data_task: at time 19155000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 00ba
[19180000.0 ps] cmd_task Write    
simsoctb.ram_chip.cmd_task: at time 19180000.0 ps INFO: Write     bank 0 col 000, auto precharge 0
simsoctb.ram_chip.data_task: at time 19207500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = ca8c
simsoctb.ram_chip.data_task: at time 19210000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = face
simsoctb.ram_chip.data_task: at time 19212500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = c0de
simsoctb.ram_chip.data_task: at time 19215000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = c0de
simsoctb.ram_chip.data_task: at time 19217500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 4242
simsoctb.ram_chip.data_task: at time 19220000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 1337
simsoctb.ram_chip.data_task: at time 19222500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 0bab
simsoctb.ram_chip.data_task: at time 19225000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 00ba
[19250000.0 ps] cmd_task Write    
simsoctb.ram_chip.cmd_task: at time 19250000.0 ps INFO: Write     bank 0 col 000, auto precharge 0
simsoctb.ram_chip.data_task: at time 19277500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 0304
simsoctb.ram_chip.data_task: at time 19280000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 0102
simsoctb.ram_chip.data_task: at time 19282500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = c0de
simsoctb.ram_chip.data_task: at time 19285000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = c0de
simsoctb.ram_chip.data_task: at time 19287500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 4242
simsoctb.ram_chip.data_task: at time 19290000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 1337
simsoctb.ram_chip.data_task: at time 19292500.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 0bab
simsoctb.ram_chip.data_task: at time 19295000.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 00ba
[19335000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 19335000.0 ps INFO: Read      bank 0 col 000, auto precharge 0
simsoctb.ram_chip.data_task: at time 19362500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 0304
simsoctb.ram_chip.data_task: at time 19365000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 0102
simsoctb.ram_chip.data_task: at time 19367500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = c0de
simsoctb.ram_chip.data_task: at time 19370000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = c0de
simsoctb.ram_chip.data_task: at time 19372500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 4242
simsoctb.ram_chip.data_task: at time 19375000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 1337
simsoctb.ram_chip.data_task: at time 19377500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 0bab
simsoctb.ram_chip.data_task: at time 19380000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 00ba
[19505000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 19505000.0 ps INFO: Read      bank 0 col 000, auto precharge 0
simsoctb.ram_chip.data_task: at time 19532500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 0304
simsoctb.ram_chip.data_task: at time 19535000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 0102
simsoctb.ram_chip.data_task: at time 19537500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = c0de
simsoctb.ram_chip.data_task: at time 19540000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = c0de
simsoctb.ram_chip.data_task: at time 19542500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 4242
simsoctb.ram_chip.data_task: at time 19545000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 1337
simsoctb.ram_chip.data_task: at time 19547500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 0bab
simsoctb.ram_chip.data_task: at time 19550000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 00ba
[19675000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 19675000.0 ps INFO: Read      bank 0 col 000, auto precharge 0
simsoctb.ram_chip.data_task: at time 19702500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 0304
simsoctb.ram_chip.data_task: at time 19705000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 0102
simsoctb.ram_chip.data_task: at time 19707500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = c0de
simsoctb.ram_chip.data_task: at time 19710000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = c0de
simsoctb.ram_chip.data_task: at time 19712500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 4242
simsoctb.ram_chip.data_task: at time 19715000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 1337
simsoctb.ram_chip.data_task: at time 19717500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 0bab
simsoctb.ram_chip.data_task: at time 19720000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 00ba
[19845000.0 ps] cmd_task Read     
simsoctb.ram_chip.cmd_task: at time 19845000.0 ps INFO: Read      bank 0 col 000, auto precharge 0
simsoctb.ram_chip.data_task: at time 19872500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 0304
simsoctb.ram_chip.data_task: at time 19875000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 0102
simsoctb.ram_chip.data_task: at time 19877500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = c0de
simsoctb.ram_chip.data_task: at time 19880000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = c0de
simsoctb.ram_chip.data_task: at time 19882500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 4242
simsoctb.ram_chip.data_task: at time 19885000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 1337
simsoctb.ram_chip.data_task: at time 19887500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 0bab
simsoctb.ram_chip.data_task: at time 19890000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 00ba
simsoctb.v:261: $finish called at 1995000000 (10fs)